Multiplexer

Schematic of a 2-to-1 Multiplexer. It can be equated to a controlled switch.

Schematic of a 1-to-2 Demultiplexer. Like a multiplexer, it can be equated to a controlled switch.

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line.^[1] A multiplexer of 2ⁿ inputs has ⌈n⌉ select lines, which are used to select which input line to send to the output.^[2] Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.^[1] A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean functions of multiple variables.

An electronic multiplexer makes it possible for several signals to share one device or resource, for example, one A/D converter or one communication line, instead of having one device per input signal.

Conversely, a demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. A multiplexer is often used with a complementary demultiplexer on the receiving end.^[1]

An electronic multiplexer can be considered as a multiple-input, single-output switch, and a demultiplexer as a single-input, multiple-output switch.^[3] The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and the short parallel side containing the output pin.^[4] The schematic on the right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right. The $sel$ wire connects the desired input to the output.

Cost saving

The basic function of a multiplexer: combining multiple inputs into a single data stream. On the receiving side, a demultiplexer splits the single data stream into the original multiple signals.

One use for multiplexers is economizing connections over a single channel, by connecting the multiplexer's single output to the demultiplexer's single input. The image to the right demonstrates this benefit. In this case, the cost of implementing separate channels for each data source is higher than the cost and inconvenience of providing the multiplexing/demultiplexing functions.

At the receiving end of the data link a complementary demultiplexer is usually required to break the single data stream back down into the original streams. In some cases, the far end system may have functionality greater than a simple demultiplexer; and while the demultiplexing still occurs technically, it may never be implemented discretely. This would be typical when: a multiplexer serves a number of IP network users; and then feeds directly into a router, which immediately reads the content of the entire link into its routing processor; and then does the demultiplexing in memory from where it will be converted directly into IP sections.

Often, a multiplexer and demultiplexer are combined together into a single piece of equipment, which is conveniently referred to as a "multiplexer". Both circuit elements are needed at both ends of a transmission link because most communications systems transmit in both directions.

In analog circuit design, a multiplexer is a special type of analog switch that connects one signal selected from several inputs to a single output.

Digital multiplexers

In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect $\scriptstyle I_{0}$ to the output while a logic value of 1 would connect $\scriptstyle I_{1}$ to the output. In larger multiplexers, the number of selector pins is equal to $\scriptstyle \left\lceil \log _{2}(n)\right\rceil$ where $\scriptstyle n$ is the number of inputs.

For example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs would require no fewer than 5 selector pins. The binary value expressed on these selector pins determines the selected input pin.

A 2-to-1 multiplexer has a boolean equation where $\scriptstyle A$ and $\scriptstyle B$ are the two inputs, $\scriptstyle S$ is the selector input, and $\scriptstyle Z$ is the output:

Z=(A\cdot {\overline {S}})+(B\cdot S)

A 2-to-1 mux

Which can be expressed as a truth table:

$\scriptstyle S$	$\scriptstyle A$	$\scriptstyle B$	$\scriptstyle Z$
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	0
1	0	1	1
1	1	0	0
1	1	1	1

Or, in simpler notation:

$\scriptstyle S$	$\scriptstyle Z$
0	A
1	B

These tables show that when $\scriptstyle S=0$ then $\scriptstyle Z=A$ but when $\scriptstyle S=1$ then $\scriptstyle Z=B$ . A straightforward realization of this 2-to-1 multiplexer would need 2 AND gates, an OR gate, and a NOT gate. While this is mathematically correct, it should be noted that a direct physical implementation would be prone to race conditions that require additional gates to suppress.^[5]

Larger multiplexers are also common and, as stated above, require $\scriptstyle \left\lceil \log _{2}(n)\right\rceil$ selector pins for $n$ inputs. Other common sizes are 4-to-1, 8-to-1, and 16-to-1. Since digital logic uses binary values, powers of 2 are used (4, 8, 16) to maximally control a number of inputs for the given number of selector inputs.

4-to-1 mux
8-to-1 mux
16-to-1 mux

The boolean equation for a 4-to-1 multiplexer is:

Z=(A\cdot {\overline {S_{0}}}\cdot {\overline {S_{1}}})+(B\cdot S_{0}\cdot {\overline {S_{1}}})+(C\cdot {\overline {S_{0}}}\cdot S_{1})+(D\cdot S_{0}\cdot S_{1})

The following 4-to-1 multiplexer is constructed from 3-state buffers and AND gates (the AND gates are acting as the decoder):

A 4:1 MUX circuit using 3 input AND and other gates

The subscripts on the $\scriptstyle I_{n}$ inputs indicate the decimal value of the binary control inputs at which that input is let through.

Chaining multiplexers

Larger Multiplexers can be constructed by using smaller multiplexers by chaining them together. For example, an 8-to-1 multiplexer can be made with two 4-to-1 and one 2-to-1 multiplexers. The two 4-to-1 multiplexer outputs are fed into the 2-to-1 with the selector pins on the 4-to-1's put in parallel giving a total number of selector inputs to 3, which is equivalent to an 8-to-1.

List of ICs which provide multiplexing

The 7400 series has several ICs that contain multiplexer(s):

IC No.	Function	Output State
74157	Quad 2:1 mux.	Output same as input given
74158	Quad 2:1 mux.	Output is inverted input
74153	Dual 4:1 mux.	Output same as input
74352	Dual 4:1 mux.	Output is inverted input
74151A	8:1 mux.	Both outputs available (i.e., complementary outputs)
74151	8:1 mux.	Output is inverted input
74150	16:1 mux.	Output is inverted input

Digital demultiplexers

Demultiplexers take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs depending on the values of the selection inputs. Demultiplexers are sometimes convenient for designing general purpose logic, because if the demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any function of the selection bits can be constructed by logically OR-ing the correct set of outputs.

If X is the input and S is the selector, and A and B are the outputs:

$A=(X\cdot {\overline {S}})$

$B=(X\cdot S)$

Example: A Single Bit 1-to-4 Line Demultiplexer

List of ICs which provide demultiplexing

Fairchild 74F138

The 7400 series has several ICs that contain demultiplexer(s):

IC No. (7400)	IC No. (4000)	Function	Output State
74139		Dual 1:4 demux.	Output is inverted input
74156		Dual 1:4 demux.	Output is open collector
74138		1:8 demux.	Output is inverted input
74238		1:8 demux.
74154		1:16 demux.	Output is inverted input
74159	CD4514/15	1:16 demux.	Output is open collector and same as input

Multiplexers as PLDs

Multiplexers can also be used as programmable logic devices, specifically to implement Boolean functions. Any Boolean function of n variables and one result can be implemented with a multiplexer with n selector inputs. The variables are connected to the selector inputs, and the function result, 0 or 1, for each possible combination of selector inputs is connected to the corresponding data input. This is especially useful in situations when cost is a factor, for modularity, and for ease of modification. If one of the variables (for example, D) is also available inverted, a multiplexer with n-1 selector inputs is sufficient; the data inputs are connected to 0, 1, D, or ~D, according to the desired output for each combination of the selector inputs.^[6]

References

1 2 3 Dean, Tamara (2010). Network+ Guide to Networks. Delmar. pp. 82–85.
↑ Debashis, De (2010). Basic Electronics. Dorling Kindersley. p. 557.
↑ Lipták, Béla (2002). Instrument engineers' handbook: Process software and digital networks. CRC Press. p. 343.
↑ Harris, David (2007). Digital Design and Computer Architecture. Penrose. p. 79.
↑ Crowe, John and Barrie Hayes-Gill (1998) Introduction to Digital Electronics pp. 111-113
↑ Donald E. Lancaster (1975). The TTL Cookbook. Howard W. Sams & Co. pp. 140–143.

External links

The dictionary definition of multiplexer at Wiktionary
Media related to Multiplexers at Wikimedia Commons

CPU technologies
Architecture	Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (Modified) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit (NPU) Convolutional neural network Load/store architecture Register memory architecture Register register architecture Endianness FIFO Zero-copy NUMA HUMA HSA Heterogeneous computing Parallel computing Amorphous computing Reconfigurable computing Cognitive computing DNA computing Peptide computing Chemical computing Organic computing Wetware computer Quantum computing Neuromorphic computing Optical computing Reversible computing Unconventional computing Hypercomputation Ternary computer Symmetric multiprocessing (SMP) Asymmetric multiprocessing (AMP) Cache hierarchy Memory hierarchy
ISA types	ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison
ISAs	x86 z/Architecture ARM MIPS Power Architecture (PowerPC) SPARC VISC Mill Itanium (IA-64) Alpha Prism SuperH Clipper VAX Unicore PA-RISC MicroBlaze
Word size	1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable
Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards
Parallel level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory
Multithreading	Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout
Flynn's taxonomy	SISD SIMD (SWAR) SIMT MISD MIMD SPMD Addressing mode
CPU performance	Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) SUPS Performance per watt Orders of magnitude (computing) Cache performance measurement and metric
Core count	Single-core processor Multi-core processor Manycore processor
Types	Central processing unit (CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor (DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit (PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module (MCM) Chip stack multi-chip modules System on a chip (SoC) Network on a chip (NoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip (PSoC)
Components	Execution unit (EU) Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Load-store unit (LSU) Fixed-point unit (FXU) Vector unit (VU) Branch predictor Branch execution unit (BEU) Instruction Decoder Instruction Scheduler Instruction Fetch Unit Instruction Dispatch Unit Instruction Sequencing Unit Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit (MMU) Input–output memory management unit (IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer (TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter-coupled logic (ECL) Transistor–transistor logic (TTL) Glue logic Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor
Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating
Hardware security	Non-executable memory (NX bit) Bounds checking (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology OmniShield Trusted Platform Module (TPM) Secure cryptoprocessor Hardware security module Hengzhi chip
Related	History of general-purpose CPUs

Authority control	GND: 4170727-8

This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.