MOS Technology CIA

Pin configuration of the 6526 CIA
Early 6526 CIA were still in costly ceramic package with gold contacts. Later versions were produced in cheaper plastic package.
CIA MOS 6526A in plastic package

The 6526/8521 Complex Interface Adapter (CIA) was an integrated circuit made by MOS Technology. It served as an I/O port controller for the 6502 family of microprocessors, providing for parallel and serial I/O capabilities as well as timers and a Time-of-Day (TOD) clock. The device's most prominent use was in the Commodore 64 and Commodore 128(D), each of which included two CIA chips. The Commodore 1570 and Commodore 1571 floppy disk drives contained one CIA each. The Amiga home computers employed two and Commodore 1581 floppy disk drive one 8520 chip, which is functionally equivalent to 6526/8521 except the simplified TOD circuitry.

Parallel I/O

The CIA had two 8-bit bidirectional parallel I/O ports. Each port had a corresponding Data Direction Register, which allowed each data line to be individually set to input or output mode. A read of these ports always returned the status of the individual lines, regardless of the data direction that had been set.

Serial I/O

An internal bidirectional 8-bit shift register enabled the CIA to handle serial I/O. The chip could accept serial input clocked from an external source, and could send serial output clocked with one of the built-in programmable timers. An interrupt was generated whenever an 8-bit serial transfer had completed. It was possible to implement a simple "network" by connecting the shift register and clock outputs of several computers together. The maximum bitrate is 500 kbit/s for the 2 MHz version.

The CIA incorporates a fix to a bug in the serial-shift register in the earlier 6522 VIA. The CIA was originally intended for use with the 1541 drive for the Commodore 64, but was not used because of the goal of VIC-20 compatibility, causing disk speeds to be as slow as on the VIC-20.[1]

Interval timers

Two programmable interval timers were available, each with sub-microsecond precision. Each timer consisted of a 16-bit read-only presettable down counter and a corresponding 16-bit write-only latch. Whenever a timer was started, the timer's latch was automatically copied into its counter, and the counter would then decrement with each clock cycle until underflow, at which an interrupt would be generated.

The timer could run in either "one-shot" mode, halting after the first interrupt, or "continuous" mode, reloading the latch value again and starting the timer cycle anew. In addition to generating interrupts, the timer output could also be gated to the second I/O port.

As configured in the Commodore 64 and Commodore 128, the CIA's timing was controlled by the phase two system clock, nominally one MHz. This meant that the timers decremented at approximately one microsecond intervals, the exact time period being determined by whether the system used the NTSC or PAL video standard. In the C-128, clock stretching was employed so the CIA's timing was unaffected by whether the system was running in SLOW or FAST mode.

It was possible to generate relatively long timing intervals by programming timer B to count timer A underflows. If both timers were loaded with the maximum interval value of 65,535, a timing interval of one hour, 11 minutes, 34 seconds would result.

Time-of-Day (TOD) Clock

A real-time clock is incorporated in the CIA, providing a timekeeping device more conducive to human needs than the microsecond precision of the interval timers. Time is kept in the American 12-hour AM/PM format. The TOD clock consists of four read/write registers: hours (with bit 7 acting as the AM/PM flag), minutes, seconds and tenths of a second. All registers read out in BCD format, thus simplifying the encoding/decoding process.

Reading from the registers will always return the time of day. In order to avoid a carry error while fetching the time, reading the hours register will immediately halt register updating, with no effect on internal timekeeping accuracy. Once the tenths register has been read, updating will resume. It is possible to read any register other than the hours register "on the fly," making the use of a running TOD clock as a timer a practical application. If the hours register is read, however, it is essential to subsequently read the tenths register. Otherwise, all TOD registers will remain "frozen."

Setting the time involves writing the appropriate BCD values into the registers. A write access to the hours register will completely halt the clock. The clock will not start again until a value has been written into the tenths register. Owing to the order in which the registers appear in the system's memory map, a simple loop is all that is required to write the registers in the correct order. It is permissible to write to only the tenths register to "nudge" the clock into action, in which following a hardware reset, the clock will start at 1:00:00.0.

In addition to its timekeeping features, the TOD can be configured to act as an alarm clock, by arranging for it to generate an interrupt request at any desired time. Due to a bug in many 6526s (see also errata below), the alarm IRQ would not always occur when the seconds component of the alarm time is exactly zero. The workaround is to set the alarm's tenths value to 0.1 seconds.

The TOD clock's internal circuitry is designed to be driven by either 50 or 60 Hz clock signal, which can be inexpensively derived from the mains power source AC, resulting in a stable timekeeper with little long-term drift. The ability to work with both power line frequencies allowed a single version of the 6526 to be used in computers operated in countries with either 50 or 60 Hz mains power lines. It is important to note that contrary to the popular belief, NTSC or PAL video standards are not directly linked to mains power frequency. Additionally, some computers did not derive their TOD clock frequency from the mains power source. For example, both NTSC and PAL variants of Commodore SX-64 use 60 Hz TOD clock supplied by a dedicated crystal. KERNAL operating system in Commodore 64 for example will determine the video standard during system startup, but tries neither to identify the supplied TOD clock frequency nor to initialise the CIAs correctly on 50 Hz driven machines. Thus, it is the responsibility of any application software that wants to use either CIA's TOD function to determine the supplied frequency and set the CIA(s) flag accordingly itself. Failure to do so may cause the clock to deviate quickly from the correct time.

The 8520 revision of the CIA, as used in the Amiga and the Commodore 1581 disk drive, modified the time-of-day clock to be a 24-bit binary counter, replacing the BCD format of the 6526. Other behavior was similar, however.

Versions

The CIA was available in 1 MHz (6526), 2 MHz (6526A) and 3 MHz (6526B) versions. The form factor was a JEDEC-standard 40-pin ceramic or plastic DIP. The 8520 CIA, with its modified time-of-day clock, was used in the Amiga computers.

Commodore embedded reduced (just 4 registers) CIA-like logic for the cost reduced Commodore 1571 inside the C128DCR (See Commodore 128) in a gate array called 5710 which also contains other functions. The 5710 CIA has the serial clock for the fast serial interface hardwired to a CIA6526 equivalent Timer A value of 5, leading to a per-bit time of 5µs on transmission. This is different from what used to be a Timer A value of 6 in the 6526 CIA in the original Commodore 1571. The 5710 CIA does not contain timer or timer control registers. It only contains two port registers and the register to control the serial shifter and its event.

Errata

In addition to the aforementioned alarm clock interrupt bug, many CIAs exhibited a defect in which the part would fail to generate a timer B hardware interrupt if the interrupt control register (ICR) was read one or two clock cycles before the time when the interrupt should have actually occurred. This defect, as well as logic errors in the Commodore provided (8 bit ) operating system, caused frequent pseudo-RS-232 errors in the Commodore 64 and Commodore 128 computers when running at higher baud rates.

References

  1. ↑ Perry, Tekla S.; Wallich, Paul (March 1985). "Design case history: the Commodore 64" (PDF). IEEE Spectrum: 48–58. ISSN 0018-9235. Archived from the original (PDF) on 2012-05-13. Retrieved 2011-11-12.
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