List of instruction sets

A list of computer central processor instruction sets: (Companies that created only a few different processors are listed at the end under "Other")

Altera

Nios II, 32-bit RISC,^[1] CPU core optimized for implementation in Altera FPGAs

AMD

AM29000, (112 Instructions) RISC^[2]
AMD extensions to x86
- 3DNow! – 3DNow! instructions (21 instructions)
- 3DNow! Extended – extended 3DNow! instructions (5 instructions)
AMD64 64-bit version of x86, a superset of Intel's IA-32

Analog Devices

ARM

ARM^[3]
- ARMv1
- ARMv2
- ARMv3
- ARMv4
- ARMv5
  - Extensions
    - Thumb^[4]
    - DSP^[5]
    - Jazelle
    - VFPv2 – vector floating point
- ARMv6
  - Extensions
    - Thumb-2^[6]
    - TrustZone^[7]
    - SIMD^[8]
- ARMv7
  - Extensions
    - Thumb-2
    - NEON – media acceleration technology^[9]
    - VFPv3
- ARMv8-A

Atmel

AVR^[10]
AVR32^[11]

CDC

DEC

PDP-1
PDP-7, predecessor PDP-4, and successor PDP-9
PDP-8 and predecessor PDP-5
PDP-10 and predecessor PDP-6, and successor DECSYSTEM-20
PDP-11
VAX
Alpha
Prism

Donald Knuth

MIX
MMIX^[12]

Hewlett-Packard

HP 2100
FOCUS
HP 3000 "Classic" CISC
PA-RISC
- PA-RISC 1.0
- PA-RISC 1.1
  - MAX-1 SIMD extensions
- PA-RISC 2.0
  - MAX-2 SIMD extensions

Hitachi (later, Renesas)

SuperH, RISC^[13]^[14]^[15]
- SH-1 (56 instructions)
- SH-2 (62 instructions)
- SH-2 DSP (154 instructions)
- SH-3 (68 instructions)
- SH-3 DSP (160 instructions)
- SH-4 (91 instructions)^[16]
- SH-5 ^[17]
SH64,^[18]
H8
- H8/300 (57 instructions) RISC like^[19]
- H8/500 (63 instructions)^[20]
- H8S/2000
- HD6309^[21]

IBM

IBM 1130/IBM 1800
IBM 1400 series/IBM 7010
IBM 1620/IBM 1710
IBM 37xx
IBM 3790
IBM 650
IBM 701
IBM 704/IBM 709/IBM 7090/IBM 7094/IBM 7040/IBM 7044
IBM 702/IBM 705/IBM 7080
IBM 7070/IBM 7072/IBM 7074
IBM 7030 Stretch
System/360 and successors
- System/370
- System/390
- z/Architecture
IBM 8100
IBM Series/1
IBM System/3
IBM System/34
IBM System/36
IBM System/38
IBM System/7
IBM AS/400/IBM System i
ROMP
Power Architecture
- POWER
- PowerPC
- PowerPC AS

Infineon

Infineon C166^[22]
Infineon C500^[23]
Infineon Technologies TriCore™

Intel

4004
8008 / Datapoint 2200
8080 (111 Instructions),^[24] 8085 (113 Instructions)^[25]
8021 (66 Instructions)^[26]
8022 (73 Instructions)^[27]
MCS-41 (8041) (87 Instructions)^[28]
MCS-48 (8048) (93 Instructions)^[29]
MCS-51 (8051)
Intel iAPX 432
Intel i860^[30]^[31]
i960
IA-64,^[32] Itanium, originated at Hewlett-Packard (HP), and later jointly developed by HP and Intel
x86, See: x86 instruction listings
- IA-32 (i386, Pentium, Athlon)
- Intel 64 64-bit version of x86, originally developed by AMD as AMD64
- Extensions^[33]
  - FPU (x87) – Floating-point-unit (FPU) instructions
  - MMX – MMX SIMD instructions
  - MMX Extended – extended MMX SIMD instructions
  - SSE – streaming SIMD extensions (SSE) instructions (70 instructions)
  - SSE2 – streaming SIMD extensions 2 instructions (144 new instructions)
  - SSE3 – streaming SIMD extensions 3 instructions (13 new instructions)
  - SSSE3 – supplemental streaming SIMD extensions (16 instructions)
  - SSE4.1 – streaming SIMD extensions 4, Penryn subset (47 instructions)
  - SSE4.2 – streaming SIMD extensions 4, Nehalem subset (7 instructions)
  - SSE4 – All streaming SIMD extensions 4 instructions (both SSE4.1 and SSE4.2)
  - SSE4a – streaming SIMD extensions 4a (AMD)
  - SSE5 – streaming SIMD extensions 5 (170 instructions)
  - XSAVE – XSAVE instructions
  - AVX – advanced vector extensions instructions
  - FMA – fused multiply-add instructions
  - AES – Advanced Encryption Standard instructions
  - CLMUL – Carry-less mtiply (PCLMULQDQ) instruction
  - Cyrix – Cyrix-specific instructions
  - AMD – AMD-specific instructions (older than K6)
  - SMM – System management mode instructions
  - SVM – Secure virtual machine instructions
  - PadLock – VIA PadLock instructions

Lattice Semiconductor

Microchip Technology

PIC microcontroller
- Mid-range PIC^[34]
- PIC16^[35]
- PIC17^[35]
- PIC18^[35]
- dsPIC30F^[36]
- dsPIC33

MIPS

MIPS
- MIPS I
- MIPS II
- MIPS III
- MIPS IV^[37]
- MIPS V
- MIPS16
- MIPS32
- MIPS64
- MDMX

Mitsubishi (later, Renesas)

Mitsubishi D10V^[38]
Mitsubishi D30V^[39]

Motorola

HC11 (62 instructions)^[40]
HC16
Motorola 6800 (107 instructions)^[41]
Motorola 6801 (98 instructions)^[42]
Motorola 6805 (86 instructions)^[43]
Motorola 6809 (94 instructions)^[44]
Motorola 68000 family
- 68000^[45]
- 68010^[46]
- 68020 and 68030
  - 68881 and 68882 FPUs
- 68040
- 68060
- 683XX
- ColdFire
88000
DSP56800^[47]

National Semiconductor

COP8
CR16
NSC800^[48]
NS320xx^[49]^[50]^[51]

Renesas

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1, 2003.

Renesas 78K0R^[52] identical with successor Renesas RL78^[53] (80 instructions divided in 15 groups)
Renesas 740 (71 instructions)
Renesas M16C (106 instructions)^[54]
Renesas M32C (108 instructions)^[55]
Renesas M32R (108 instructions)^[56]
Renesas V850^[57]

Sun Microsystems

SPARC^[58]
- SPARC-V7
- SPARC-V8
- SPARC-V9
  - Extensions
    - VIS
picoJava
MAJC

Texas Instruments

Xilinx

Zilog

Other

ARC (also ARCompact, ARCtangent)^[67]
Burroughs B5000/B6000/B7000 series
Cambridge Consultants XAP series
Cray supercomputers
DLX^[68]
EISC (AE32K)
Elliott Automation
Fairchild Clipper^[69]
GI Microelectronics SP0256 - Speech processor^[70]
INMOS Transputer^[71]
LC-3
Maxim MAXQ
MOS Technology 6502^[72]
OpenRISC open ISA originally developed by the OpenCores community
Raptor-16^[73]
RCA CDP1802^[74]
RCA Spectra 70 (System/360 compatible in user mode ("problem state"), not compatible in kernel mode ("supervisor state"))
RISC-V open ISA introduced in 2010
Samsung SAM8
Signetics 2650^[75]
STMicroelectronics ST10
Ubicom IP2000
UNIVAC 1100/2200 series
XMOS XCore^[76]
Xtensa^[77]

References

↑ Nios II Instruction Set Reference
↑ "Evaluating and Programming the 29K RISC Family" (PDF). AMD. Archived from the original (PDF) on 2007-09-27.
↑ ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd
↑ ARM Thumb
↑ ARM DSP
↑ ARM Thumb-2
↑ ARM TrustZone
↑ ARM SIMD
↑ ARM - NEON media acceleration technology
↑ AVR
↑ "AVR32 Architecture Document", Atmel.
↑ MMIX
↑ SH-Microcomputer User's Manual (Renesas)
↑ SuperH (SH) 64-Bit RISC Series (SuperH).
↑ http://www.renesas.com/products/mpumcu/superh/child/sh_cpu_child.jsp
↑ SH-4 32-bit CPU Core Architecture
↑ 64-Bit RISC Series SH-5 System Architecture, Volume 1: System
↑ SuperH 64 bit RISC Series Architecture Manual (SuperH, Inc.)
↑ H8/300
↑ H8/500 Series Programming Manual (Hitachi M21T001)
↑ Instruction set reference for 6809/6309 (PDF) By Chris Lomont
↑ "Infineon C166 and Instruction Set Manual", Infineon
↑ "Infineon C500 Architecture and Instruction Set", Infineon
↑ 8080a
↑ 8085a
↑ 8021
↑ 8022
↑ 8041
↑ 8048
↑ i860 Microprocessor Programmer's Reference Manual or i860 Microprocessor Architecture
↑ i860 Microprocessor Datasheet
↑ IA-64 Architecture Handbook
↑ Yasm User Manual – Execution Modes and extensions, Chapter 18. x86 Architecture
↑ Section 29. Instruction Set
1 2 3 Instruction set: PIC
↑ dsPIC30F Programmer’s Reference Manual
↑ MIPS IV Instruction set
↑ D10V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.)
↑ D30V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.
↑
↑ 6800 MICROPROCESSOR Instruction Set Summary (April 1985)
↑ 6801/68701 Single-Chip MICROCOMPUTER Instruction Set Summary (April 1985)
↑ 6805 MICROPROCESSOR Instruction Set Summary (April 1985)
↑ 6809 MICROPROCESSOR Instruction Set Summary (April 1985)
↑ http://www.textfiles.com/programming/CARDS/68000
↑ http://www.textfiles.com/programming/CARDS/68010
↑ DSP56800 Family Manual
↑ NSC800 MICROPROCESSOR Instruction Set Summary (April 1985)
↑ NS16032 MICROPROCESSOR Instruction Set Summary (July 1985)
↑ NS32016 MICROPROCESSOR Instruction Set Summary (July 1985)
↑ NS32032 MICROPROCESSOR Instruction Set Summary (July 1985)
↑ "78K0R Microcontrollers User's Manual: Instructions". Renesas. January 2011. pp. 191–192. Archived from the original (PDF) on 2012-03-16. Retrieved 2011-08-02.
↑ "RL78 family User’s Manual: Software". Renesas. January 2011. pp. 198–199. Archived from the original (PDF) on 2012-03-16. Retrieved 2011-08-02.
↑ Renesas M16C
↑ Renesas M32C
↑ Renesas M32R
↑ NEC V850 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual from NEC. Ltd
↑ The Sparc Architecture Manual
↑ 9900 MICROPROCESSOR Instruction Set Summary
↑ 9940 MICROPROCESSOR Instruction Set Summary
↑ 9980 MICROPROCESSOR Instruction Set Summary
↑ MSP430 User's Manual, document slau049d, Texas Instrument, Inc
↑ "Xilinx UG129 PicoBlaze 8-bit Embedded Microcontroller User Guide, Chapter 3, PicoBlaze Instruction Set", Xilinx
↑ Z80 MICROPROCESSOR Instruction Set Summary (April 1985)
↑ Z8601/02/03/11/12/13 Single-Chip MICROCOMPUTER Instruction Set Summary (April 1985)
↑ Z8001/Z8002 MICROPROCESSOR Instruction Set Summary
↑ ARC Programmers Reference Manual, ARC International
↑ Sailer, Philip M.; Kaeli, David R.. The DLX Instruction Set Architecture Handbook. Morgan Kaufmann. ISBN 1-55860-371-9.
↑ "The Clipper processor: instruction set architecture and implementation"
↑ SPO256 - Speech processor
↑ INMOS Transputer
↑ 6502 MICROPROCESSOR Instruction Set Summary
↑ Raptor-16
↑ CDP1802 COSMAC Microprocessor Instruction Set Summary (April 1985)
↑ 2650 MICROPROCESSOR Instruction Set Summary
↑ "XMOS XS1 Instruction Set Architecture"
↑ Xtensa Instruction Set Architecture (ISA) Reference Manual

External links

Programming Textfiles: Bowen's Instruction Summary Cards

CPU technologies
Architecture	Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (Modified) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit (NPU) Convolutional neural network Load/store architecture Register memory architecture Register register architecture Endianness FIFO Zero-copy NUMA HUMA HSA Heterogeneous computing Parallel computing Amorphous computing Reconfigurable computing Cognitive computing DNA computing Peptide computing Chemical computing Organic computing Wetware computer Quantum computing Neuromorphic computing Optical computing Reversible computing Unconventional computing Hypercomputation Ternary computer Symmetric multiprocessing (SMP) Asymmetric multiprocessing (AMP) Cache hierarchy Memory hierarchy
ISA types	ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison
ISAs	x86 z/Architecture ARM MIPS Power Architecture (PowerPC) SPARC VISC Mill Itanium (IA-64) Alpha Prism SuperH Clipper VAX Unicore PA-RISC MicroBlaze
Word size	1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable
Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards
Parallel level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory
Multithreading	Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout
Flynn's taxonomy	SISD SIMD (SWAR) SIMT MISD MIMD SPMD Addressing mode
CPU performance	Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) SUPS Performance per watt Orders of magnitude (computing) Cache performance measurement and metric
Core count	Single-core processor Multi-core processor Manycore processor
Types	Central processing unit (CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor (DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit (PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module (MCM) Chip stack multi-chip modules System on a chip (SoC) Network on a chip (NoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip (PSoC)
Components	Execution unit (EU) Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Load-store unit (LSU) Fixed-point unit (FXU) Vector unit (VU) Branch predictor Branch execution unit (BEU) Instruction Decoder Instruction Scheduler Instruction Fetch Unit Instruction Dispatch Unit Instruction Sequencing Unit Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit (MMU) Input–output memory management unit (IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer (TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter-coupled logic (ECL) Transistor–transistor logic (TTL) Glue logic Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor
Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating
Hardware security	Non-executable memory (NX bit) Bounds checking (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology OmniShield Trusted Platform Module (TPM) Secure cryptoprocessor Hardware security module Hengzhi chip
Related	History of general-purpose CPUs

This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.