Josh Fisher

Josh Fisher

Josh Fisher in 2014.
Born (1946-07-22) July 22, 1946 [1]
Bronx, NY, USA [1]
Fields Computer Architecture, Compiling, Embedded Systems
Institutions Yale University, Multiflow Computer, Hewlett-Packard Laboratories (retired)
Alma mater Courant Institute of Mathematical Sciences (New York University)
Known for The Invention of VLIW Architectures, Instruction-level Parallelism, Trace Scheduling, Co-Founder of Multiflow Computer
Notable awards Eckert-Mauchly Award, (IEEE/ACM 2003)
B. Ramakrishna Rau Award (IEEE-CS 2012)
Connecticut Entrepreneur of the Year (1987)
Presidential Young Investigator's Award (NSF 1984)

Joseph A "Josh" Fisher is an American computer scientist noted for his work on VLIW architectures, compiling, and instruction-level parallelism, and for the founding of Multiflow Computer. He is a Hewlett-Packard Senior Fellow (Emeritus).[2]

Biography

Fisher holds a BA (1968) in mathematics (with honors) from New York University and obtained a Master's and PhD degree (1979) in Computer Science from The Courant Institute of Mathematics of New York University.[1]

Fisher joined the Yale University Department of Computer Science in 1979 as an assistant professor, and was promoted to associate professor in 1983. In 1984 Fisher left Yale to found Multiflow Computer with Yale colleagues John O'Donnell and John Ruttenberg. Fisher joined HP Labs upon the closing of Multiflow in 1990. He directed HP Labs in Cambridge, MA USA from its founding in 1994, and became an HP Fellow (2000) and then Senior Fellow (2002) upon the inception of those titles at Hewlett-Packard. Fisher retired from HP Labs in 2006.

Fisher is married (1967) to Elizabeth Fisher; they have a son, David Fisher, and a daughter, Dora Fisher.[3]

Work

Trace Scheduling

In his Ph.D. dissertation, Fisher created the Trace Scheduling compiler algorithm and coined the term Instruction-level parallelism to characterize VLIW, superscalar, dataflow and other architecture styles that involve fine-grained parallelism among simple machine-level instructions. Trace scheduling was the first practical algorithm to find large amounts of parallelism between instructions that occupied different basic blocks. This greatly increased the potential speed-up for instruction-level parallel architectures.

The VLIW architecture style

Because of the difficulty of applying trace scheduling to idiosyncratic systems (such as 1970s-era DSPs) that in theory should have been suitable targets for a trace scheduling compiler, Fisher put forward the VLIW architectural style. VLIWs are normal computers, designed to run compiled code and used like ordinary computers, but offering large amounts of instruction-level parallelism scheduled by a trace scheduling or similar compiler. VLIWs are now used extensively, especially in embedded systems. The most popular VLIW cores have sold in quantities of several billion processors. [4] [5] [6] [7]

Multiflow Computer

Multiflow was founded to commercialize trace scheduling and VLIW architectures, then widely thought to be impractical. Multiflow's technical success and the dissemination of its technology and people had a great effect on the future of computer science and the computer industry.[3]

Awards and honors

Writings

References

  1. 1 2 3 Joseph A Fisher vita
  2. ↑ Hewlett-Packard Senior Fellow Biography.
  3. 1 2 http://www.MultiflowTheBook.com Multiflow Computer: A Startup Odyssey.
  4. ↑ The Hexagon VLIW The Hexagon is a 4-issue VLIW.
  5. ↑ Qualcomm Announces Its 2012 Superchip: 28nm Snapdragon S4, 10/12/2011 by John Oram. The article states that Hexagons have been in Snapdragon chips since 2006.
  6. ↑ Estimate of Snapdragon volumes.
  7. ↑ The ST231. The ST231 is rumored to have been sold in quantities upwards of 1 billion cores, used mostly in digital video.
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