Immersion lithography

In immersion lithography, light travels down through a system of lenses and then a pool of water before reaching the photoresist on top of the wafer.

Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits (ICs) that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is increased by a factor equal to the refractive index of the liquid. Current immersion lithography tools use highly purified water for this liquid, achieving feature sizes below 45 nanometers.[1] ASML, Canon, and Nikon are currently the only manufacturers of immersion lithography systems. The idea for Immersion lithography was first proposed and realized in the 1980s. [2]

Benefits of immersion lithography

The ability to resolve features in optical lithography is directly related to the numerical aperture of the imaging equipment, the numerical aperture being the sine of the maximum refraction angle multiplied by the refractive index of the medium through which the light travels. The lenses in the highest resolution "dry" photolithography scanners focus light in a cone whose boundary is nearly parallel to the wafer surface. As it is impossible to increase resolution by further refraction, additional resolution is obtained by inserting an immersion medium with a higher index of refraction between the lens and the wafer. The blurriness is reduced by a factor equal to the refractive index of the medium. For example, for water immersion using ultraviolet light at 193 nm wavelength, the index of refraction is 1.44.

The resolution enhancement from immersion lithography is about 30-40% (depending on materials used). However, the depth of focus, or tolerance in wafer topography flatness, is reduced compared to the corresponding "dry" tool at the same resolution.

The successful emergence of immersion lithography comes not just from its ability to extend resolution and depth of focus, but also from its timely introduction to the industry (e.g., IBM, AMD) between 65 nm and 45 nm nodes.

Intel's 32 nm process uses second-generation high-k, metal gate technology, but this will be the first time Intel has deployed immersion lithography.[3]

Manufacturing issues

The main obstacle to adoption of immersion lithography systems has been defects and other possible sources of yield loss. Early studies focused on the elimination of bubbles in the immersion fluid, temperature and pressure variations in the immersion fluid, and immersion fluid absorption by the photoresist.[4] Degassing the fluid, carefully constraining the fluid thermodynamics and carefully treating the top layer of photoresist have been key to the implementation of immersion lithography. Defects intrinsic to immersion lithography have been identified.[5] Reducing particle generation due to the water dispensing unit was found to reduce the incidence of defects. Water also has been shown to extract acid from photoresist.[6] Specifically, photoacid generators (PAGs) are extracted into the water, which produce acid upon radiation exposure. This must be managed to ensure the lens is not corroded by the acid or contaminated by the extracted agents, and the photoresist is not chemically altered to the point of being defective. Still, since diffusion of contaminants is expected to be much slower in water than in air or vacuum, consideration of optics contamination actually favors immersion lithography. Water-soaked photoresist also has been demonstrated to produce very satisfactory images.[7]

In addition, 193 nm light has been known to ionize water,[8] producing solvated electrons, which may spread and react with the photoresist, affecting the resolution performance.

The above defect concerns have led to considerations of using a topcoat layer directly on top of the photoresist. This topcoat would serve as a barrier for chemical diffusion between the liquid medium and the photoresist. In addition, the interface between the liquid and the topcoat would be optimized for watermark reduction. At the same time, defects from topcoat use should be avoided.

As scanning speeds typically approach 500 mm/s for high-volume manufacturing, the actual resist-water contact time in any given exposure area is minimal. Hence the main concerns for defects are water left behind (watermarks) and loss of resist-water adhesion (air gap). The hydrophobicity of the surface and the water delivery/removal method are therefore the key areas to address. Other areas where defects may be enhanced are at the wafer edge, where the water has to do an "about-face" (reverse motion). It is important for the water not to pick up defects from the wafer backside.

Generally, implementation into manufacturing is only considered when defect yields reach a mature level, e.g., comparable to dry lithography levels.

Future of immersion lithography

As of 2007, many companies, including IBM, UMC, Toshiba, and TI are ramping for the 45 nm node using immersion lithography. AMD's Fab 36 is already equipped for using immersion lithography for its 65 nm, 45 nm and 32 nm node technologies.[9] AMD has also made preparations for advanced design for manufacturability (DFM), including layout regularity and double patterning at the 22 nm node, using immersion lithography.[10] For the 32 nm node in 2009, Intel will begin using immersion lithography as well. Intel has confirmed that since EUV will not be available, it will extend 193 nm immersion lithography to the 22 nm node [11] and 15 nm node.[12] Intel has already outlined a path to use 193 nm immersion lithography down to 11 nm node.[13] IBM has also stated that it will be using immersion lithography for the 22 nm node, since no other alternative is available at this time.[14]

Polarization effects in immersion lithography. For pitches where immersion lithography is relevant, the polarization will affect the intensity inside the photoresist. This example is for 56 nm half-pitch.

Enhancements necessary to extend the technology beyond the 32 nm node are currently being investigated. Such enhancements include the use of higher refractive-index materials in the final lens, immersion fluid, and photoresist, in order to improve the resolution with single patterning.

Currently, the most promising high-index lens material is lutetium aluminum garnet, with a refractive index of 2.14. High-index immersion fluids are approaching refractive index values of 1.7. These new developments allow the optical resolution to approach ~30 nm. However, it is expected that at some point below 40 nm, current photoresists will limit further scaling.[15] Polarization effects due to high angles of interference in the photoresist also have to be considered as features approach 40 nm.[16] Hence, new photoresists will need to be developed for sub-40 nm applications.

On the other hand, double patterning has received interest recently since it can potentially increase the half-pitch resolution by a factor of 2. This could allow the use of immersion lithography tools beyond the 32 nm node, potentially to the 16 nm node. While double patterning improves pitch resolution, it must rely on non-lithographic methods, such as trimming, to actually reduce the feature size, possibly by as much as 50%.

On March 23, 2012, with the release of the Ivy Bridge chip, Intel's Senior Fellow Mark Bohr stated that the company will be able to extend its current immersion process to the 14-nm and even 10-nm chips before EUV would be necessary. He did not mention specific techniques that will be utilized.

References

  1. ↑ DailyTech - IDF09 Intel Demonstrates First 22nm Chips Discusses Die Shrink Roadmap
  2. ↑ Burn J. Lin (1987). "The future of subhalf-micrometer optical lithography". Microelectronic Engineering 6, 31–51
  3. ↑ Intel to use immersion lithography for first time at 32 nm
  4. ↑ M. Switkes et al., J. Vac. Sci. & Tech. B vol. 21, pp. 2794-2799 (2003).
  5. ↑ U. Okoroanyanwu et al., "Defectivity in water immersion lithography," Microlithography World, November 2005.
  6. ↑ J. C. Taylor et al., SPIE vol. 5376, pp. 34-43 (2004).
  7. ↑ A. K. Raub et al., J. Vac. Sci. & Tech. B vol. 22, pp. 3459-3464 (2004).
  8. ↑ A. Iwata et al., Chem. Lett., vol. 22, 1939 (1993).
  9. ↑ D. Grose, 2007 Technology Analyst Day, July 26, 2007.
  10. ↑ "DFM, Design Restrictions Enable Double Patterning," Semiconductor International, 12/1/2007 article link.
  11. ↑ Intel: 'EUV Facts Don't Add Up' for 22 nm in 2011
  12. ↑ SPIE: Intel to extend immersion to 11-nm
  13. ↑ Presentation by Y. Borodovsky, "Marching to the Beat of Moore's Law," SPIE Microlithography 2006.
  14. ↑ IBM sees immersion at 22nm, pushes out EUV
  15. ↑ U. Okoroanyanwu and J. H. Lammers, Future Fab International, Issue 17 (2004).
  16. ↑ C. Wagner et al., Proc. SPIE vol. 4000, pp. 344-357 (2000).
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