Integrated circuit packaging

Cross section of a dual in-line package. This type of package houses a small semiconducting die, with nanowires attaching the die to the lead frames, allowing for electrical connections to be made to a PCB.

In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the tiny block of semiconducting material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board.

In the integrated circuit industry, the process is often referred to as packaging. Other names include semiconductor device assembly, assembly, encapsulation or sealing.

The packaging stage is followed by testing of the integrated circuit.

The term is sometimes confused with electronic packaging, which is the mounting and interconnecting of integrated circuits (and other components) onto printed-circuit boards.

Design considerations

Electrical

The current-carrying traces that run out of the die, through the package, and into the printed circuit board (PCB) have very different electrical properties compared to on-chip signals. They require special design techniques and need much more electric power than signals confined to the chip itself. Therefore, it is important that the materials used as electrical contacts exhibit characteristics like low resistance, low capacitance and low inductance.[1] Both the structure and materials must prioritize signal transmission properties, while minimizing any parasitic elements that could negatively affect the signal.

Controlling these characteristics is becoming increasingly important as the rest of technology begins to speed up. Packaging delays have the potential to make up almost half of a high-performance computer's delay, and this bottleneck on speed is expected to increase.[1]

Mechanical and thermal

The integrated circuit package is responsible for keeping the chip safe from all sorts of potential damage. The package must resist physical breakage, provide an airtight seal to keep out moisture, and also provide effective heat dissipation away from the chip. At the same time, it must have effective means of connecting to a PCB, which can change drastically depending on the package type.[1] The materials used for the body of the package are typically either plastic (thermoset or thermoplastic) or ceramic. They both can offer a high thermal conductivity and decent mechanical strength. Ceramic generally has more preferable characteristics, but is more expensive.[2]

Increasing the surface area of the package allows for better heat transfer via convection, and some packages utilize metallic fins to enhance heat transfer even further at the cost of valuable space. Larger sizes also allow for a greater number of mechanical connections.[1] However, these factors are balanced out by the fact that the package generally needs to be kept as small as possible.

Economic

Cost is a major limiting factor for many designs. Choices such as package material and level of precision must be balanced by the economic viability of the end product. Depending on the needs of the system, opting for lower-cost materials is often an acceptable solution to economic constraints. Typically, an inexpensive plastic package can dissipate heat up to 2W, which is sufficient for many simple applications, though a similar ceramic package can dissipate up to 50W in the same scenario.[1] As the chips inside the package get smaller and faster, they also tend to get hotter. As the subsequent need for more effective heat dissipation increases, the cost of packaging rises along with it. Generally, the smaller and more complex the package needs to be, the more expensive it is to manufacture.[2]

History

Small-outline integrated circuit. This package has 16 "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 inches.

The earliest integrated circuits were packaged in ceramic flat packs, which the military used for many years for their reliability and small size.[3] Commercial circuit packaging quickly moved to the dual in-line package (DIP), first in ceramic and later in plastic.[4] In the 1980s VLSI pin counts exceeded the practical limit for DIP packaging, leading to pin grid array (PGA) and leadless chip carrier (LCC) packages.[5] Surface mount packaging appeared in the early 1980s and became popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by small-outline integrated circuit — a carrier which occupies an area about 30 – 50% less than an equivalent DIP, with a typical thickness that is 70% less.[5]

Early USSR made integrated circuit. The tiny block of semiconducting material (the "die"), is enclosed inside the round, metallic case (the "package").

The next big innovation was the area array package, which places the interconnection terminals throughout the surface area of the package, providing a greater number of connections than previous package types where only the outer perimeter is used. The first area array package was a ceramic pin grid array package.[1] Not long after, the plastic ball grid array (BGA), another type of area array package, became one of the most commonly used packaging techniques.[6]

In the late 1990s, plastic quad flat pack (PQFP) and thin small-outline packages (TSOP) replaced PGA packages as the most common for high pin count devices,[1] though PGA packages are still often used for microprocessors. However, industry leaders Intel and AMD transitioned in the 2000s from PGA packages to land grid array (LGA) packages.[7]

Ball grid array (BGA) packages have existed since the 1970s, but evolved into Flip-chip ball grid array packages (FCBGA) in the 1990s. FCBGA packages allow for much higher pin count than any existing package types. In an FCBGA package, the die is mounted upside-down (flipped) and connects to the package balls via a substrate that is similar to a printed-circuit board rather than by wires. FCBGA packages allow an array of input-output signals (called Area-I/O) to be distributed over the entire die rather than being confined to the die periphery.[8]

Traces out of the die, through the package, and into the printed circuit board have very different electrical properties, compared to on-chip signals. They require special design techniques and need much more electric power than signals confined to the chip itself.

Recent developments consist of stacking multiple dies in single package called SiP, for System In Package, or three-dimensional integrated circuit. Combining multiple dies on a small substrate, often ceramic, is called an MCM, or Multi-Chip Module. The boundary between a big MCM and a small printed circuit board is sometimes blurry.[9]

Common package types

Operations

Die attachment is the step during which a die is mounted and fixed to the package or support structure (header).[10] For high-powered applications, the die is usually eutectic bonded onto the package, using e.g. gold-tin or gold-silicon solder (for good heat conduction). For low-cost, low-powered applications, the die is often glued directly onto a substrate (such as a printed wiring board) using an epoxy adhesive.

The following operations are performed at the packaging stage, as broken down into bonding, encapsulation, and wafer bonding steps. Note that this list is not all-inclusive and not all of these operations are performed for every package, as the process is highly dependent on the package type.

See also

References

  1. 1 2 3 4 5 6 7 Rabaey, Jan (2007). Digital Integrated Circuits (2nd Edition). Prentice Hall, Inc. ISBN 978-0130909961.
  2. 1 2 Greig, William (2007). Integrated Circuit Packaging, Assembly and Interconnections. Springer Science & Business Media. ISBN 9780387339139.
  3. ↑ "Quality Support". www.ametek-ecp.com. Retrieved 2016-03-30.
  4. ↑ Dummer, G.W.A. Electronic Inventions and Discoveries (2nd ed). Pergamon Press. ISBN 0-08-022730-9.
  5. 1 2 Baker, R. Jacob (2010). CMOS: Circuit Design, Layout, and Simulation, Third Edition. Wiley-IEEE. ISBN 978-0-470-88132-3.
  6. ↑ Ken Gilleo (2003). Area array packaging processes for BGA, Flip Chip, and CSP. McGraw-Hill Professional. p. 251. ISBN 0-07-142829-1.
  7. ↑ "Land Grid Array (LGA) Socket and Package Technology" (PDF). Intel. Retrieved April 7, 2016.
  8. ↑ Riley, George (2009-01-30). "Flipchips: Tutorial #1". Archived from the original on January 30, 2009. Retrieved 2016-04-07.
  9. ↑ R. Wayne Johnson, Mark Strickland and David Gerke, NASA Electronic Parts and Packaging Program. "3-D Packaging: A Technology Review." June 23, 2005. Retrieved July 31, 2015
  10. ↑ L. W. Turner (ed), Electronics Engineers Reference Book, Newnes-Butterworth, 1976, ISBN 0-408-00168-2, pages 11-34 through 11-37
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