Fireplane

Fireplane is a computer internal interconnect created by Sun Microsystems.

The Fireplane interconnect architecture is an evolutionary development of Sun's previous Ultra Port Architecture (UPA). It was introduced in October 2000 as the processor I/O interconnect in the Sun Blade 1000 workstation, followed in early 2001 by its use in the Sun Fire and Sun Fire 15K series enterprise servers.[1] These coincided with the popular expansion of the web in the dot com boom and a shift of Sun's main market from Unix workstations to datacenter servers such as the Starfire, supporting high traffic web sites.

Peak performance (in the Sun Blade 1000) reached 67.2 GBytes/second or a sustained 9.6 GB/s (2.4 GB/s for each processor).[2]

Each generation of Sun architecture had involved upgraded processors and matching upgrades to the bus or interconnect architectures that supported them.[3][4] By this time, fast access to memory was becoming more important than simple CPU instruction speed for overall performance. Multiprocessors, shared memory, memory caching and switching between CPU and memory were technologies necessary to achieve this.

The Sun Fire 15K series frame allows 18 combined processor and memory expander boards. Each board comprises four processors, four memory modules and I/O processors. The Fireplane interconnect uses 18×18 crossbar switches to connect between them.[5] Overall peak bandwidth through the interconnect is 43 Gbytes per second.

As memory architectures increase in complexity, maintaining cache coherence becomes a greater problem than simple connectivity. Fireplane represents a substantial advance over previous interconnects in this aspect.[6] It combines both snoopy cache[7] and point-to-point directory-based models to give a two-level cache coherence model.[8] Snoopy buses are used primarily for single buses with small numbers of processors; directory models are used for larger numbers of processors.[4] Fireplane combines both, to give a scalable shared memory architecture.

Each expander board implements snooping across the board, with directory coherence across the interconnect. Each board is considered as a 'snooping coherence domain'. Small to mid-sized Fireplane systems, up to 24 processors, use a single coherence domain.[6] Larger systems with more processors use multiple coherence domains across their backplane interconnect.[6] Competing systems from makers such as SGI or the HP Superdome series[9] use only a single level of coherency support and so require the more complex directory coherence to be used throughout.

Fireplane used for smaller servers and workstations is optimised for their single domain performance. They use an increased system clock by 50% to 150 MHz. Snoops per clock cycle are also doubled from one half to one. Together these allow a snooping bandwidth of 150 million addresses per second.[5]

References

  1. ↑ "SUN FIRE 4810 Midframe Server" (PDF).
  2. ↑ Gian-Paolo Musumeci; Michael Kosta Loukides (2002). "System Performance Tuning" (2nd ed.). O'Reilly Media. pp. 69–70. ISBN 059600284X.
  3. ↑ Charlesworth, Alan (2001). "The Sun Fireplane System Interconnect" (PDF). ACM. p. 2.
  4. 1 2 Farrell, Ryan (October 2005). "The Sun Fireplane System Interconnect" (PDF). p. 2.
  5. 1 2 "1.3.1 Sun Fireplane Interconnect Architecture". Sun Fire 15K/12K Systems Introduction.
  6. 1 2 3 Charlesworth 2001, p. 3
  7. ↑ "Snooping". PCI System Architecture. Addison-Wesley Professional. 1995. p. Appendix A. ISBN 0201309742.
  8. ↑ Charlesworth 2001, p. 1
  9. ↑ "HP Superdome White Paper" (PDF). Hewlett Packard. September 2000. Archived from the original (PDF) on 2001-06-12.
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