FeiTeng (processor)

FeiTeng
Max. CPU clock rate 0.8 GHz to 1.0 GHz
Instruction set SPARCv9

FeiTeng (飞腾, fēiténg) is the name of several computer central processing units designed and produced in China for supercomputing applications.[1]

FeiTeng-1000 is the third generation CPU from the YinHeFeiTeng (银河飞騰, YHFT) family. This CPU family has been developed by a team directed by NUDT's Professor Xing Zuocheng.[2] The first generation was binary compatible with the Intel Itanium 2. The second generation, the FT64, was a system on a chip with CPU and 64-bit stream processor; FT64 chips were used in YinHe (银河) supercomputers as accelerators.[3]

FeiTeng-1000

FeiTeng-1000 is manufactured with 65 nm technology and contains 350 million gates. Its clock frequency is 0.8–1 GHz. It is compatible with the SPARCv9 instruction set architecture.[4]

Each chip contains 8 cores and is capable of executing 64 threads. There are 3 HyperTransport channels for coherent links, 4 DDR3 memory controllers and a 8x PCIe 2.0 link. [5]

The Tianhe-1A supercomputer uses 2,048 FeiTeng 1000 processors.[6] Tianhe-1A has a theoretical peak performance of 4.701 petaflops, also employing 7,168 Nvidia Tesla M2050 GPUs and 14,336 Intel Xeon X5670 CPUs in addition to FT1000 processors.[5][7] The FeiTeng-1000 is an eight-core processor based on the SPARC system and is used to operate service nodes on the Tianhe-1.[1][5]

A 2012 report for the European High Performance Computing service stated that FeiTeng used the work of the OpenSPARC project.[8]

Galaxy FT-1500

Tianhe-2 supercomputer uses 4096 processors Galaxy FT-1500 with 16 cores, OpenSPARC architecture based and 65 W TDP. They are made with 40 nm technology, processor cores work at 1.8 GHz[9] Peak performance of FT-1500 is 115–144 GFLOPS; every core may execute up to 8 interleaving threads and supports 256-bit wide SIMD vector operations including Fused Mul-Add (FMA). Cache of this SoC works at 2 GHz frequency, there are 16 KB L1i, 16 KB L1d, 512 KB L2 per core, and shared 4 MB L3 cache. L3 cache has 4 segments (1 segment per block of 4 CPU cores), each of 1 MB with 32-way associative. Cache uses directory-based cache coherency protocol. FT-1500 also has:[10]

FT-1500A

FT-1500A is a ARM64 SoC designed by Phytium, which includes 16 cores of ARMv8 processor, a 32-lane PCIe host, 2 GMAC on-chip ethernet controller and a GICv3 interrupt controller with ITS support.[11]

See also

References

  1. 1 2 Patrick Thibodeau (2010-11-04). "U.S. says China building 'entirely indigenous' supercomputer". Computerworld. Retrieved 2016-06-17.
  2. ↑ "HKUST - Department of Electronic & Computer Engineering". Ee.ust.hk. 2011-10-20. Retrieved 2016-06-17.
  3. ↑ "HKUST - Department of Electronic & Computer Engineering". ust.hk. Retrieved 17 June 2016.
  4. ↑ "China introduces homegrown Feiteng CPU server - People's Daily Online". English.people.com.cn. 2011-03-25. Retrieved 2016-06-17.
  5. 1 2 3 The TianHe-1A Supercomputer: Its Hardware and Software by Xue-Jun Yang, Xiang-Ke Liao, et al in the Journal of Computer Science and Technology, Volume 26, Number 3, May 2011, pp. 344-351 "Archived copy". Archived from the original on 2011-06-21. Retrieved 2012-02-08.
  6. ↑ "Top100爆冷门 天河一号力压星云再夺魁-IT168 服务器专区". Server.it168.com. 2010-10-28. Retrieved 2016-06-17.
  7. ↑ "China builds world's fastest supercomputer". ZDNet UK. 29 October 2010.
  8. ↑ "INFRA-2010-2.3.1 – First Implementation Phase of the European High Performance Computing (HPC) service PRACE" (PDF). Prace-project.eu. Retrieved 2016-06-17.
  9. ↑ Dongarra, Jack (3 June 2013). "Visit to the National University for Defense Technology Changsha, China" (PDF). Netlib. (in English) page 9
  10. ↑ MilkyWay-2 supercomputer: system and application. Xiangke LIAO, Liquan XIAO, Canqun YANG, Yutong LU. Front. Comput. Sci., 2014, 8(3): 345–356 DOI:10.1007/s11704-014-3501-3 (September 6, 2013)
  11. ↑ "'[PATCH 0/3] Add support for Phytium FT-1500A SoC' - MARC". marc.info. Retrieved 17 June 2016.
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