FLAGS register

The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16 bits wide. Its successors, the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller predecessors.

The fixed bits at bit positions 1, 3 and 5, and carry, parity, adjust, zero and sign flags are inherited from an even earlier architecture, 8080. The adjust flag used to be called auxiliary carry bit in 8080 and half-carry bit in the Zilog Z80 architecture.

FLAGS

Intel x86 FLAGS register[1]
Bit # Abbreviation Description Category
FLAGS
0 CF Carry flag Status
1 Reserved, always 1 in EFLAGS [2]  
2 PF Parity flag Status
3 Reserved  
4 AF Adjust flag Status
5 Reserved  
6 ZF Zero flag Status
7 SF Sign flag Status
8 TF Trap flag (single step) Control
9 IF Interrupt enable flag Control
10 DF Direction flag Control
11 OF Overflow flag Status
12-13 IOPL I/O privilege level (286+ only), always 1 on 8086 and 186 System
14 NT Nested task flag (286+ only), always 1 on 8086 and 186 System
15 Reserved, always 1 on 8086 and 186, always 0 on later models  
EFLAGS
16 RF Resume flag (386+ only) System
17 VM Virtual 8086 mode flag (386+ only) System
18 AC Alignment check (486SX+ only) System
19 VIF Virtual interrupt flag (Pentium+) System
20 VIP Virtual interrupt pending (Pentium+) System
21 ID Able to use CPUID instruction (Pentium+) System
22 Reserved  
23 Reserved  
24 Reserved  
25 Reserved  
26 Reserved  
27 Reserved  
28 Reserved  
29 Reserved  
30 Reserved  
31 Reserved  
RFLAGS
32-63 Reserved  

USE

The POPF, POPFD, and POPFQ instructions read from the stack, the first 16, 32, and 64 bits of the flags register, respectively. POPFD was introduced with the i386 architecture and POPFQ with the x64 architecture. In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but not PUSHFD/POPFD.[3]

The following assembly code changes the direction flag (DF):

pushf ; Pushes the current flags onto the stack
pop ax ; Pop the flags from the stack into ax register
push ax ; Push them back onto the stack for storage
xor ax, 400h ; toggle the DF flag only, keep the rest of the flags
push ax ; Push again to add the new value to the stack
popf ; Pop the newly pushed into the FLAGS register
; ... Code here ...
popf ; Pop the old FLAGS back into place

In practical software, the cld and std instructions are used to clear and set the direction flag, respectively. Some instructions in assembly language use the FLAGS register. The conditional jump instructions use certain flags to compute. For example, jz uses the zero flag, jc uses the carry flag and jo uses the overflow flag. Other conditional instructions look at combinations of several flags.

Determination of processor type

Testing if certain bits in the FLAGS register are changeable allows determining what kind of processor is installed. For example, the alignment flag can only be changed on the 486 and above, so if it can be changed then the CPU is a 486 or higher. These methods of processor detection were not made obsolete by the CPUID instruction introduced with the Intel Pentium, as CPUID is not implemented in these older CPUs.

See also

References

  1. ↑ Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). 1. May 2012. pp. 3–21.
  2. ↑ Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 1. Dec 2016. p. 78.
  3. ↑ Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 2B. May 2012. pp. 4–349,4–432.
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