High-level synthesis

High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior.[1] Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from e.g. clock-level timing. Early HLS explored a variety of input specification languages.,[2] although recent research and commercial applications generally accept synthesizable subsets of ANSI C/C++/SystemC/MATLAB. The code is analyzed, architecturally constrained, and scheduled to create a register-transfer level (RTL) hardware description language (HDL), which is then in turn commonly synthesized to the gate level by the use of a logic synthesis tool. The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.[3]

Hardware design can be created at a variety of levels of abstraction. The commonly used levels of abstraction are gate level, register-transfer level (RTL), and algorithmic level.

While logic synthesis uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation.[4] The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation.

History

Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the finite-state machine. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path.

First generation behavioral synthesis was introduced by Synopsys in 1994 as Behavioral Compiler[5] and used Verilog or VHDL as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys end-of-lifed Behavioral Compiler.[6]

In 2004, there emerged a number of next generation commercial high-level synthesis products (also called behavioral synthesis or algorithmic synthesis at the time) which provided synthesis of circuits specified at C level to a register transfer level (RTL) specification.[7] Synthesizing from the popular C language offered accrued abstraction, expressive power and coding flexibility while tying with existing flows and legacy models. This language shift, combined with other technical advances was a key enabler for successful industrial usage. High-level synthesis tools are used for complex ASIC and FPGA design.

High-level synthesis was primarily adopted in Japan and Europe in the early years. As of late 2008, there was an emerging adoption in the United States.[8]

Source input

The most common source inputs for high-level synthesis are based on standard languages such as ANSI C/C++, SystemC and MATLAB.

High-level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with an FIR filter written using the "double" floating type, before he or she can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete.[9] Normally the tools infer from the high level code a Finite State Machine and a Datapath that implement arithmetic operations.

Process stages

The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.[10]

Functionality

In general, an algorithm can be performed over many clock cycles with few hardware resources, or over fewer clock cycles using a larger number of ALUs, registers and memories. Correspondingly, from one algorithmic description, a variety of hardware microarchitectures can be generated by an HLS compiler according to the directives given to the tool. This is the same trade off of execution speed for hardware complexity as seen when a given program is run on conventional processors of differing performance, yet all running at roughly the same clock frequency.

Architectural constraints

Synthesis constraints for the architecture can automatically be applied based on the design analysis.[3] These constraints can be broken into

Interface synthesis

Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO.[11]

Vendors

Data reported on recent Survey[12]

Status Compiler Owner License Input Output Year Domain TestBench FP FixP
Announced A++ Altera Commercial C/C++ VHDL/Verilog 2016 All ? ? ?
In Use AUGH TIMA Lab. Academic C subset VHDL 2012 All Yes No No
eXCite Y Explorations Commercial C VHDL/Verilog 2001 All Yes No Yes
Bambu PoliMi Academic C VHDL/Verilog 2012 All Yes Yes No
Bluespec BlueSpec Inc. Commercial BSV SystemVerilog 2007 All No No No
CHC Altium Commercial C subset VHDL/Verilog 2008 All No Yes Yes
CoDeve-loper Impulse Accelerated Commercial Impulse-C VHDL 2003 Image Streaming Yes Yes No
Stratus Cadence Commercial C/C++ SystemC RTL 2015 All Yes No Yes
Cyber- Workbench NEC Commercial BDL, SystemC VHDL/Verilog 2011 All Cycle/ Formal Yes Yes
Catapult Mentor (Siemens business) Commercial C, C++, SystemC VHDL/Verilog 2004 Streaming No No Yes
DWARV TU. Delft Academic C subset VHDL 2012 All Yes Yes Yes
GAUT U. Bretagne Academic C/C++ VHDL 2010 DSP Yes No Yes
Hastlayer Lombiq Technologies Commercial .NET (C#/C++/F#...) VHDL 2015 .NET Yes No Yes
LegUp U. Toronto Academic C Verilog 2011 All Yes Yes No
MaxCompiler Maxeler Commercial MaxJ RTL 2010 DataFlow No Yes No
ROCCC Jacquard Comp. Commercial C subset VHDL 2010 Streaming No Yes No
Symphony C Synopsys Commercial C/C++ VHDL/Verilog /SystemC 2010 All Yes No Yes
VivadoHLS

(formerly AutoPilot from AutoESL[13])

 Xilinx Commercial C/C++/SystemC VHDL/Verilog/SystemC 2013 All Yes Yes Yes
Kiwi U. Cambridge Academic C# Verilog 2008 .NET No Yes Yes
N/A CHiMPS U. Washington Academic C VHDL 2008 All No No No
gcc2verilog U. Korea Academic C Verilog 2011 All No No No
HercuLeS Ajax Compilers Commercial C/NAC VHDL 2012 All Yes Yes Yes
Shang ? U. Illinois C Verilog 2013 All Yes ? ?
Trident Los Alamos NL Academic C subset VHDL 2007 Scientific No Yes No
Abandoned AccelDSP Xilinx Commercial MATLAB VHDL/Verilog 2006 DSP Yes Yes Yes
C2H Altera Commercial C VHDL/Verilog 2006 All No No No
CtoVerilog U. Haifa Academic C Verilog 2008 All No No No
DEFACTO U. South Cailf. Academic C RTL 1999 DSE No No No
Garp U. Berkeley Academic C subset bitstream 2000 Loop No No No
MATCH U. Northwest Academic MATLAB VHDL 2000 Image No No No
Napa-C Sarnoff Corp. Academic C subset VHDL/Verilog 1998 Loop No No No
PipeRench U.Carnegie M. Academic DIL bistream 2000 Stream No No No
SA-C U. Colorado Academic SA-C VHDL 2003 Image No No No
SeaCucumber U. Brigham Y. Academic Java EDIF 2002 All No Yes Yes
SPARK U. Cal. Irvine Academic C VHDL 2003 Control No No No

See also

References

  1. ↑ "High-Level Synthesis - Springer". Springerlink.com. Retrieved 2016-10-03.
  2. ↑ IEEE Xplore High-Level Synthesis: Past, Present, and Future DOI 10.1109/MDT.2009.83
  3. 1 2 "The 'why' and 'what' of algorithmic synthesis". EE Times. Retrieved 2016-10-03.
  4. ↑ "C-Based Rapid Prototyping for Digital Signal Processing" (PDF). UBS University, France. Retrieved 2016-10-03.
  5. ↑ "Publications and Presentations". Bdti.com. Retrieved 2016-10-03.
  6. ↑ "Behavioral synthesis crossroad". EE Times. Retrieved 2016-10-03.
  7. ↑
  8. ↑
  9. ↑ Multiple Word-Length High-Level Synthesis EURASIP Journal on Embedded Systems
  10. ↑ "A look inside behavioral synthesis". EE Times. Retrieved 2016-10-03.
  11. ↑
  12. ↑ Nane, R.; Sima, V. M.; Pilato, C.; Choi, J.; Fort, B.; Canis, A.; Chen, Y. T.; Hsiao, H.; Brown, S. (2016-01-01). "A Survey and Evaluation of FPGA High-Level Synthesis Tools". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. PP (99): 1–1. ISSN 0278-0070. doi:10.1109/TCAD.2015.2513673.
  13. ↑ "Xilinx buys high-level synthesis EDA vendor". EE Times. 2011-02-05. Retrieved 2016-10-03.
  14. ↑ "MathWorks – Makers of MATLAB and Simulink". Mathworks.com. Retrieved 2016-10-03.
  15. ↑ "SystemC based ESL methodologies - SystemC based ESL methodologies". Circuitsutra.com. Retrieved 2016-10-03.
  16. ↑ John M. at a major ERP & DBMS Corporation (2016-08-29). "QuickPlay: Bringing FPGA Computing to the Masses". Quickplay.io. Retrieved 2016-10-03.
  17. ↑
  18. ↑ "CyberWorkBench: Products". NEC. Retrieved 2016-10-03.
  19. ↑
  20. ↑
  21. ↑ "Nikolaos Kavvadias - HercuLeS high-level synthesis tool". Nkavvadias.com. Retrieved 2016-10-03.
  22. ↑ "Synopsys buys Synfora assets". EE Times. Retrieved 2016-10-03.
  23. ↑ "The xPilot System". Cadlab.cs.ucla.edu. Retrieved 2016-10-03.
  24. ↑ "vSyn.ru". vSyn.ru. 2016-06-16. Retrieved 2016-10-03.
  25. ↑ "Hardware design for all". Synflow. Retrieved 2016-10-03.

Further reading

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