Advanced Power Management

Advanced power management (APM) is an API developed by Intel and Microsoft and released in 1992^[1] which enables an operating system running an IBM-compatible personal computer to work with the BIOS (part of the computer's firmware) to achieve power management.

Revision 1.2 was the last version of the APM specification, released in 1996. ACPI is intended as the successor to APM. Microsoft dropped support for APM in Windows Vista. The Linux kernel still mostly supports APM, with the last fully functional APM support shipping in 3.3.

Overview

The layers in APM

APM uses a layered approach to manage devices. APM-aware applications (which include device drivers) talk to an OS-specific APM driver. This driver communicates to the APM-aware BIOS, which controls the hardware. There is the ability to opt out of APM control on a device-by-device basis, which can be used if a driver wants to communicate directly with a hardware device.

Communication occurs both ways; power management events are sent from the BIOS to the APM driver, and the APM driver sends information and requests to the BIOS via function calls. In this way the APM driver is an intermediary between the BIOS and the operating system.

Power management happens in two ways; through the above-mentioned function calls from the APM driver to the BIOS requesting power state changes, and automatically based on device activity.

Power management events

There are 12 power events (such as standby, suspend and resume requests, and low battery notifications), plus OEM-defined events, that can be sent from the APM BIOS to the operating system. The APM driver regularly polls for event change notifications.

Power Management Events:^[1]

Name	Code	Comment
System Standby Request Notification	0x0001
System Suspend Request Notification	0x0002
Normal Resume System Notification	0x0003
Critical Resume System Notification	0x0004
Battery Low Notification	0x0005
Power Status Change Notification	0x0006
Update Time Notification	0x0007
Critical System Suspend Notification	0x0008
User System Standby Request Notification	0x0009
User System Suspend Request Notification	0x000A
System Standby Resume Notification	0x000B
Capabilities Change Notification	0x000C	Due to setup or device insertion/removal

Power management functions:^[1]

Name	Code	Comment
APM Installation Check	0x00
APM Real Mode Interface Connect	0x01
APM Protected Mode 16-bit Interface Connect	0x02	Avoids real or virtual86 mode.
APM Protected Mode 32-bit Interface Connect	0x03	Avoids real or virtual86 mode.
APM Interface Disconnect	0x04
CPU Idle	0x05	Requests system suspend. 0) Clock halted until timer tick interrupt. 1) Slow clock^[1]
CPU Busy	0x06	Driver tells system APM to restore clock speed of the CPU.
Set Power State	0x07	Set system or device into Suspend/Standby/Off state.
Enable/Disable Power Management	0x08
Restore APM BIOS Power-On Defaults	0x09
Get Power Status	0x0A	Supports AC status "On backup power". And battery status.
Get PM Event	0x0B	Checks for APM events. Shall be called once per second.
Get Power State	0x0C
Enable/Disable Device Power Management	0x0D
APM Driver Version	0x0E
Engage/Disengage Power Management	0x0F	APM management for a specific device.
Get Capabilities	0x10
Get/Set/Disable Resume Timer	0x11
Enable/Disable Resume on Ring Indicator	0x12
Enable/Disable Timer Based Requests	0x13
OEM APM Installation Check	0x80	Tells if APM BIOS supports OEM hardware dependent functions.
OEM APM Function	0x80	Access to OEM specific functions.

APM functions

There are 21 APM function calls defined that the APM driver can use to query power management statuses, or request power state transitions. Example function calls include letting the BIOS know about current CPU usage (the BIOS may respond to such a call by placing the CPU in a low-power state, or returning it to its full-power state), retrieving the current power state of a device, or requesting a power state change.

Power states

The APM specification defines system power states and device power states.

System power states

APM defines five power states for the computer system:

Full On: The computer is powered on, and no devices are in a power saving mode.
APM Enabled: The computer is powered on, and APM is controlling device power management as needed.
APM Standby: Most devices are in their low-power state, the CPU is slowed or stopped, and the system state is saved. The computer can be returned to its former state quickly (in response to activity such as the user pressing a key on the keyboard).
APM Suspend: Most devices are powered off, but the system state is saved. The computer can be returned to its former state, but takes a relatively long time. (Hibernation is a special form of the APM Suspend state).
Off: The computer is turned off.

Device power states

APM also defines power states that APM-aware hardware can implement. There is no requirement that an APM-aware device implement all states.

The four states are:

Device On: The device is in full power mode.
Device Power Managed: The device is still powered on, but some functions may not be available, or may have reduced performance.
Device Low Power: The device is not working. Power is maintained so that the device may be 'woken up'.
Device Off: The device is powered off.

CPU

The CPU core (defined in APM as the CPU clock, cache, system bus and system timers) is treated specially in APM, as it is the last device to be powered down, and the first device to be powered back up. The CPU core is always controlled through the APM BIOS (there is no option to control it through a driver). Drivers can use APM function calls to notify the BIOS about CPU usage, but it is up to the BIOS to act on this information; a driver cannot directly tell the CPU to go into a power saving state.

References

1 2 3 4 "Advanced Power Management (APM) BIOS Interface Specification Revision 1.2 February 1996 Intel/Microsoft". 090429

External links

APM V1.2 Specification (RTF file).
This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.

Computer processor power management technologies

Standards

Techniques

Implementations

Power Saving	AMD Cool'n'Quiet (desktop) AMD PowerNow! (laptop) Intel SpeedStep Transmeta LongRun VIA LongHaul
Performance	Intel Turbo Boost AMD Turbo Core
Graphics	AMD PowerPlay AMD PowerTune

CPU technologies
Architecture	Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (Modified) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit (NPU) Convolutional neural network Load/store architecture Register memory architecture Register register architecture Endianness FIFO Zero-copy NUMA HUMA HSA Heterogeneous computing Parallel computing Amorphous computing Reconfigurable computing Cognitive computing DNA computing Peptide computing Chemical computing Organic computing Wetware computer Quantum computing Neuromorphic computing Optical computing Reversible computing Unconventional computing Hypercomputation Ternary computer Symmetric multiprocessing (SMP) Asymmetric multiprocessing (AMP) Cache hierarchy Memory hierarchy
ISA types	ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison
ISAs	x86 z/Architecture ARM MIPS Power Architecture (PowerPC) SPARC VISC Mill Itanium (IA-64) Alpha Prism SuperH Clipper VAX Unicore PA-RISC MicroBlaze
Word size	1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable
Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards
Parallel level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory
Multithreading	Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout
Flynn's taxonomy	SISD SIMD (SWAR) SIMT MISD MIMD SPMD Addressing mode
CPU performance	Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) SUPS Performance per watt Orders of magnitude (computing) Cache performance measurement and metric
Core count	Single-core processor Multi-core processor Manycore processor
Types	Central processing unit (CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor (DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit (PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module (MCM) Chip stack multi-chip modules System on a chip (SoC) Network on a chip (NoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip (PSoC)
Components	Execution unit (EU) Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Load-store unit (LSU) Fixed-point unit (FXU) Vector unit (VU) Branch predictor Branch execution unit (BEU) Instruction Decoder Instruction Scheduler Instruction Fetch Unit Instruction Dispatch Unit Instruction Sequencing Unit Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit (MMU) Input–output memory management unit (IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer (TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter-coupled logic (ECL) Transistor–transistor logic (TTL) Glue logic Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor
Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating
Hardware security	Non-executable memory (NX bit) Bounds checking (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology OmniShield Trusted Platform Module (TPM) Secure cryptoprocessor Hardware security module Hengzhi chip
Related	History of general-purpose CPUs

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