Gemini Guidance Computer

Gemini Guidance Computer
Gemini Guidance Computer in National Air and Space Museum
Invented by	IBM Federal Systems Division
Manufacturer	IBM Federal Systems Division
Introduced	1965 (1965)
Discontinued	1966 (1966)
Type	Avionics Guidance Computer
Processor	Discrete IC RTL based
Frequency	7.143 kilohertz clock
Memory	39-bit words memory, each composed of three 13-bit syllables, 4096 words of memory, in a ferrite core array.
Ports	Modular Display Keyboard (MDK), Modular Display Readout (MDR), Attitude Control and Maneuver Electronics (ACME), Inertial Measurement Unit (IMU), Horizon Sensors, Time Reference System (TRS)^[1]
Power consumption	28V DC
Weight	58.98 pounds (26.75 kg)
Dimensions	18.9"(H)×14.5"(W)×12.75"(D)

The Gemini Guidance Computer (sometimes Gemini Spacecraft On-Board Computer (OBC)) was a digital, serial computer designed for Project Gemini, America's second manned space project.^[2] The computer, which facilitated the control of mission maneuvers, was designed by the IBM Federal Systems Division.^[3]

Functionality

The Gemini Guidance Computer was responsible for the following functions:^[3]^[2]

Ascent - serves as a backup guidance system. The switchover is manually controlled by the astronauts
Orbital flight - provides a navigation capability to the astronauts to determine the time of retrofire and to select the landing site for safe reentry in the case of an emergency. (on extended missions ground data may become unavailable when ground data network rotates out of the orbital plane.)
Rendezvous - serves as primary reference by providing guidance information to the astronauts. The orbit parameters are determined by the ground tracking which are then sent to the spacecraft; the guidance computer was responsible for processing the information along with sensed spacecraft attitude. The information was presented to the astronauts in terms of spacecraft coordinates.
Reentry - feeds commands directly to the reentry control system for automatic reentry or provides the guidance information to the astronauts for manual reentry.

Specs

The computer was architecturally similar to the Saturn Launch Vehicle Digital Computer, in particular in the instruction set;^[4] however its circuit integration was less advanced.^[5] The GGC weighed 58.98 pounds (26.75 kg) and was powered by 28V DC. During a short power outage it could be powered by the Auxiliary Computer Power Unit (ACPU)
39-bit words memory, each composed of three 13-bit syllables^[4]
ferrite core memory of 4096 words^[6]
Two's complement integer arithmetic
7.143 kilohertz clock (140 μs per instruction); all instructions took a single cycle except for multiplication and division

References

↑ http://www.ibiblio.org/apollo/Gemini.html#Peripheral_Devices
1 2 McDonnell Corporation, NASA Project Gemini Familiarization Manual, 1965, vol. 2, pp. 8.7,8.45.
1 2 8. J. C. Hundley and R. A. Watson, "A Digital Computer in Orbital Flight," TR 63-825-892, IBM Federal Systems Division, Owego, New York, October 1964.
1 2 "Gemini Spacecraft Computer (OBC): Layout of Memory Words". 2016 [2011]. Archived from the original on 2016-05-28. Retrieved 2016-05-28.
↑ LVDC board reverse engineering project
↑ Computers in Spaceflight: The NASA Experience, chapter one

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Guidance computers
On crewed spacecraft	Apollo Abort Guidance System Apollo Guidance Computer Gemini Guidance Computer IBM TC-1 IBM AP-101
On launch vehicles	ATHENA computer ASC-15 Universal Space Guidance System Saturn Launch Vehicle Digital Computer
Category:Guidance computers

CPU technologies
Architecture	Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (Modified) Dataflow TTA Cellular Artificial neural network Machine learning Deep learning Neural processing unit (NPU) Convolutional neural network Load/store architecture Register memory architecture Register register architecture Endianness FIFO Zero-copy NUMA HUMA HSA Heterogeneous computing Parallel computing Amorphous computing Reconfigurable computing Cognitive computing DNA computing Peptide computing Chemical computing Organic computing Wetware computer Quantum computing Neuromorphic computing Optical computing Reversible computing Unconventional computing Hypercomputation Ternary computer Symmetric multiprocessing (SMP) Asymmetric multiprocessing (AMP) Cache hierarchy Memory hierarchy
ISA types	ASIP CISC RISC EDGE (TRIPS) VLIW (EPIC) MISC OISC NISC ZISC Comparison
ISAs	x86 z/Architecture ARM MIPS Power Architecture (PowerPC) SPARC VISC Mill Itanium (IA-64) Alpha Prism SuperH Clipper VAX Unicore PA-RISC MicroBlaze
Word size	1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable
Execution	Instruction pipelining Bubble Operand forwarding Out-of-order execution Register renaming Speculative execution Branch predictor Memory dependence prediction Hazards
Parallel level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory
Multithreading	Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout
Flynn's taxonomy	SISD SIMD (SWAR) SIMT MISD MIMD SPMD Addressing mode
CPU performance	Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) SUPS Performance per watt Orders of magnitude (computing) Cache performance measurement and metric
Core count	Single-core processor Multi-core processor Manycore processor
Types	Central processing unit (CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor (DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit (PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module (MCM) Chip stack multi-chip modules System on a chip (SoC) Network on a chip (NoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip (PSoC)
Components	Execution unit (EU) Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Load-store unit (LSU) Fixed-point unit (FXU) Vector unit (VU) Branch predictor Branch execution unit (BEU) Instruction Decoder Instruction Scheduler Instruction Fetch Unit Instruction Dispatch Unit Instruction Sequencing Unit Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit (MMU) Input–output memory management unit (IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer (TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate Combinational logic Sequential logic Emitter-coupled logic (ECL) Transistor–transistor logic (TTL) Glue logic Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor
Power management	APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating
Hardware security	Non-executable memory (NX bit) Bounds checking (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology OmniShield Trusted Platform Module (TPM) Secure cryptoprocessor Hardware security module Hengzhi chip
Related	History of general-purpose CPUs

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