22 nanometer

Semiconductor manufacturing processes
10 µm – 1971 6 µm – 1974 3 µm – 1977 1.5 µm – 1982 1 µm – 1985 800 nm – 1989 600 nm – 1994 350 nm – 1995 250 nm – 1997 180 nm – 1999 130 nm – 2001 90 nm – 2004 65 nm – 2006 45 nm – 2008 32 nm – 2010 22 nm – 2012 14 nm – 2014 10 nm – 2017 7 nm  – ~2018 5 nm – ~2020
Half-nodes

The 22 nanometer (22 nm) node is the process step following the 32 nm in CMOS semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first introduced by semiconductor companies in 2008 for use in memory products, while first consumer-level CPU deliveries started in April 2012.

The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.

20 nanometer is an intermediate half-node die shrink based on the 22 nanometer process.

The 22 nm process was superseded by commercial 14 nm technology in 2014.

Technology demos

On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm².^[1] The cell was printed using immersion lithography.^[2]

The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25 nm gate length would be typical for the 22 nm node.

On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer and announced that chips with 22 nm technology would be available in the second half of 2011.^[3] SRAM cell size is said to be 0.092 μm², smallest reported to date.

On January 3, 2010, Intel and Micron Technology announced the first in a family of 25 nm NAND devices.

On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a FinFET technology called 3-D Tri-Gate.^[4]

IBM's POWER8 processors are produced in a 22 nm SOI process.^[5]

Shipping devices

Flash memory

On August 31, 2010, Toshiba announced that it was shipping 24 nm flash memory NAND devices.^[6]

In 2010, Hynix Semiconductor announced that it has used a 26 nm manufacturing process to produce a flash device with 64 Gbit capacity; Intel Corp. and Micron Technology had by then already developed the technology themselves.^[7]

Processors

On April 23, 2012, Intel Core i7 and Intel Core i5 processors based on Intel's Ivy Bridge 22 nm technology for series 7 chipsets went on sale worldwide.^[8] Volume production of 22 nm processors began more than six months earlier, as confirmed by former Intel CEO Paul Otellini on October 19, 2011.^[9]

On June 3, 2013, Intel started shipping Intel Core i7 and Intel Core i5 processors based on Intel's Haswell microarchitecture in 22 nm Tri-Gate FinFET technology for series 8 chipsets.^[10]

References