VEX prefix

The VEX prefix (from "vector extensions") and VEX coding scheme are comprising an extension to the x86 and x86-64 instruction set architecture for microprocessors from Intel, AMD and others.

Features

The VEX coding scheme allows the definition of new instructions and the extension or modification of previously existing instruction codes. This serves the following purposes:

The VEX prefix replaces the most commonly used instruction prefix bytes and escape codes. In many cases, the number of prefix bytes and escape bytes that are replaced is the same as the number of bytes in the VEX prefix, so that the total length of the VEX-encoded instruction is the same as the length of the legacy instruction code. In other cases, the VEX-encoded version is longer or shorter than the legacy code. In 32-bit mode VEX encoded instructions can only access the first 8 YMM/XMM registers; the encodings for the other registers would be interpreted as the legacy LDS and LES instructions that are not supported in 64-bit mode.

The two-byte VEX prefix contains the following components:

The three-byte VEX prefix additionally contains:

Technical description

Intel 64 instruction format using VEX prefix
# of bytes 0,2,3 1 1 0,1 0,1,2,4 0,1
[Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]

The VEX coding scheme uses a code prefix consisting of 2 or 3 bytes which is added to existing or new instruction codes.[1]

In x86 architecture, instructions with a memory operand may use the ModR/M byte which specifies the addressing mode. This byte has three bit fields:

The base-plus-index and scale-plus-index forms of 32-bit addressing (encoded with r/m=100 and mod <>11) require another addressing byte, the SIB byte. It has the following fields:

To use 64-bit addressing and additional registers present in the x86-64 architecture, the REX prefix has been introduced which provides additional space for encoding addressing modes. Bit-field W expands the operand size to 64 bits, R expands reg, B expands r/m or reg (depending on the opcode format used), and X and B expand index and base in the SIB byte. However REX prefix is encoded quite inefficiently, wasting half of its 8 bits.

VEX encoding
3-byte VEX
7 6 5 4 3 2 1 0
Byte 0 1 1 0 0 0 1 0 0
Byte 1 m4 m3 m2 m1 m0
Byte 2 W 3 2 1 0 L p1 p0
2-byte VEX
7 6 5 4 3 2 1 0
Byte 0 1 1 0 0 0 1 0 1
Byte 1 3 2 1 0 L p1 p0

The VEX prefix provides a compact representation of the REX prefix, as well as various other prefixes, to expand the addressing mode, register enumeration and operand size and width:

The VEX opcode bytes, C4h and C5h, are the same as that used by the LDS and LES instructions. These instructions are not supported in 64-bit mode, while in 32-bit mode a following ModRM byte can not be of the form 11xxxxxx (which would specify a register operand). Various bits are inverted to ensure that the second byte of a VEX prefix is always of this form in 32-bit mode.

Instructions that need more than three operands have an extra suffix byte specifying one or two additional register operands. Instructions coded with the VEX prefix can have up to five operands. At most one of the operands can be a memory operand; and at most one of the operands can be an immediate constant of 4 or 8 bits. The remaining operands are registers.

The AVX instruction set is the first instruction set extension to use the VEX coding scheme. The AVX instructions have up to four operands. The AVX instruction set allows the VEX prefix to be applied only to instructions using the SIMD XMM registers. However, the VEX coding scheme has space for applying the VEX prefix to other instructions as well in future instruction sets.

Legacy SIMD instructions with a VEX prefix added are equivalent to the same instructions without VEX prefix with the following differences:

Instructions that use the whole 256-bit YMM register should not be mixed with non-VEX instructions that leave the upper half of the register unchanged, for reasons of efficiency.

History

References

  1. Intel Corporation (January 2009). "Intel Advanced Vector Extensions Programming Reference".
  2. "128-Bit SSE5 Instruction Set". AMD Developer Central. Retrieved 2009-06-02.
  3. Hruska, Joel (November 14, 2008). "AMD Fusion now pushed back to 2011". Ars Technica.
  4. "Intel Software Network". Intel. Retrieved 2008-04-05.
  5. "AMD and Intel incompatible - What to do?". AMD Developer Forums. Retrieved 2012-08-10.
  6. "AMD64 Architecture Programmer’s Manual Volume 4: 128-Bit and 256-Bit Media Instructions" (PDF). AMD. December 22, 2010.
  7. "Striking a balance". Dave Christie, AMD Developer blogs. Retrieved 2012-08-10.
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