Saraju Mohanty
Saraju Mohanty | |
---|---|
Prof. Saraju Mohanty in 2012 | |
Born | Odisha, India |
Residence | Denton, Texas, USA |
Nationality | USA |
Alma mater |
University of South Florida (USF), Tampa Indian Institute of Science (IISc), Bangalore Orissa University of Agriculture and Technology (OUAT), Bhubaneswar |
Occupation |
Professor, Author, Scientist, Engineer Computer engineer Faculty University of North Texas |
Known for | Mixed-Signal Systems, Nanoelectronics Systems, Metamodeling, Design for X, High-level synthesis (HLS), Hardware-assisted Digital watermarking |
Notable work | Nanoelectronic Mixed-Signal System Design, McGraw-Hill, 2015, ISBN 978-0071825719 |
Spouse(s) | Dr. Uma Choppali |
Honors |
Chair, Technical Committee on VLSI (TCVLSI), IEEE Computer Society (IEEE-CS). |
Website |
www |
Saraju Mohanty is a Professor and the director of the NanoSystem Design Laboratory (NSDL) at the Department of Computer Science and Engineering (CSE), at the University of North Texas (UNT) in Denton, Texas.[1][2] Prof. Mohanty is a world-renowned researcher in the areas of "Low-Power High-Performance Nanoelectronics Systems" and "hardware-assisted Digital watermarking".[3] He has made significant research contributions to Analogue electronics and Mixed-signal integrated circuit Computer-aided design (CAD) and Electronic design automation (EDA), nanoelectronic technology based High-level synthesis (HLS), and hardware-assisted Digital watermarking. He is the Chair of the Technical Committee on Very Large Scale Integration or Technical Committee on VLSI (TCVLSI), IEEE Computer Society (IEEE-CS) since September 2014.[4][5] He is a senior member of both the Institute of Electrical and Electronics Engineers (IEEE) and the Association for Computing Machinery (ACM). He is an inventor of 4 US patents in the areas of his research. Prof. Mohanty has published 200 papers and 3 books in the areas of his research.[6][7][8] The scientific articles of Prof. Mohanty are significant contributions to the engineering discipline, scientific community, and society.[9][10][11] He received 2016 PROSE Award for best Textbook in Physical Sciences & Mathematics from the AAP for his book titled "Nanoelectronic Mixed-Signal System Design". His research contributions are well-cited by researchers in different parts of the globe as evident from his Google Scholar metrics.[12] His research has been well-funded by various agencies such as the NSF, the SRC, and the Air Force.[13][14] Prof. Mohanty is a very popular professor among students as a professor who cares for them and offers quality materials in a simplified manner.[15]
Notable Scientific Contributions
Contributions to Analog Electronics and Mixed-Signal Circuits
Saraju Mohanty has introduced several novel approaches for ultra-fast design space exploration and optimization of nanoelectronic integrated circuits which can result in energy-efficient, robust, and nanoscale variation-tolerant Analog electronics circuits as well as Mixed-signal integrated circuits. The key feature of these ultra-fast design flows is the need for only two manual layout (or physical design) iterations which saves significant design effort. These ultra-fast design flows rely on accurate metamodels of the analog and mixed-signal circuit components. His research significantly advances the state-of-the art in Design for Excellence (DfX) or Design for X, such as Design for Variability (DfV) and Design for Cost (DfC).[16] The metamodel assisted ultra-fast design optimization flows can perform layout optimization of the components of analog/mixed-signal System on a chip (AMS-SoC) with very minimal design effort. This due to the 1,000X speedup caused by such techniques. As a specific example, a nanoelectronics technology based phase-locked loop (PLL) which needs several days of design cycle just for analog simulation with full-blown parasitics can be optimally designed in substantially shorter times (less than one day).[17] [18] The ultra-fast and accurate methodologies can lead to robust and low-cost consumer electronics such as smart mobile phones making them cheaper and available to larger segments of the population.
Contributions to High-Level Synthesis
Saraju Mohanty is one of the key contributors to nanoscale CMOS or nanoelectronic technology based High-level synthesis (HLS) or architecture-level synthesis.[19][20][21] His nanoelectronic-based High-level synthesis techniques addresses the issue of process variations, the primary issue of nanoelectronic technology, during the high-level synthesis itself before the digital design moves to the detailed and lower levels of design abstractions, such as logic-level or transistor-level.[22] This is a significant effort saver for digital design engineers as the digital design is statistically optimized at the higher-level of abstraction. His HLS techniques produce Register-transfer level descriptions which not only meet traditional specifications, but are also robust against nanoscale process-variations. His HLS techniques are also the first ones to address transient power dissipation or power fluctuation during high-level synthesis, thus distinguishing power-aware design and battery-aware design at the higher levels of design abstractions. This is a very important contribution for digital circuits targeted towards portable AMS-SoCs. Additionally, his research projects in the area of security aware HLS, is one of the upcoming fields in the area of digital integrated circuits and VLSI-CAD. Security aware HLS is an effort to generate datapath designs during HLS that consider security at behavioral level. This is a very important research area as it considers reliability as design specification from the highest design abstraction level. Security aware HLS is also specifically important for mission critical applications such as in military/army where hardware security is crucial for trustworthy hardware design.
Contributions to Digital Watermarking
Saraju Mohanty is a pioneer in hardware-assisted Digital watermarking for real-time copy protection and digital rights management (DRM). He has invented the concept of Secure Digital Camera (SDC) for real-time Digital rights management (DRM) at the source end of the multimedia content.[23][24] [25] The SDC has quite diverse applications where still image or video digital cameras are needed, such as secure Digital Video Broadcasting, secure Video Surveillance, electronic passport, and identity card processing. The secure digital camera (SDC) has been well-adopted by various researchers worldwide. In the process it has led to diverse implementations in various platforms by many researchers worldwide.[26][27] [28] Dr. Mohanty is the designer of the earliest and unique energy-efficient digital watermarking chips.[29] An earliest watermarking chip designed by him can perform invisible digital watermarking at the spatial domain and has capability of both robust and fragile watermarking depending on the choice of the user.[30] A unique digital watermarking chip designed by Saraju Mohanty that can perform both visible watermarking and invisible watermarking is the lowest power consuming watermarking chip available at present.
Professional Leadership
Editorial Board
- Member of the editorial board of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
- Senior Editor of the IEEE Consumer Electronics Magazine (MCE).[31]
- Founding Editor-in-Chief of the VLSI Circuits and Systems Letter (VCAL), IEEE-CS TCVLSI.[32]
- Member of the editorial board of the IET Circuits, Devices and Systems (CDS).[33]
- Member of the editorial board of the Elsevier The VLSI Integration Journal (Integration).[34]
- Member of the editorial board of the ASP Journal of Low Power Electronics (JOLPE).[35]
- Member of the editorial board of the Elsevier International Journal on Computers and Electrical Engineering (CEE), 2010-2014.
Guest Editor
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) on Circuit and System Design Automation for Internet of Things, 2016.[36]
- IEEE Transactions on Nanotechnology (TNANO) on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing, 2016.[37]
- ACM Journal on Emerging Technologies in Computing Systems (JETC) on Nanoelectronic Circuit and System Design Methods for Mobile Computing Era, 2016.[38]
- Elsevier The VLSI Integration Journal (Integration) on Hardware Assisted Techniques for IoT and Bigdata Applications, 2016.[39]
- IEEE Access Journal (Access) on Security and Reliability Aware System Design for Mobile Computing Systems, 2016.[40]
- IEEE Transactions on Emerging Topics in Computing (TETC) on Circuit and System Design Methodologies for Emerging Technologies, 2015.[41]
- Springer Circuits, Systems, and Signal Processing Journal (CSSP) on Advanced Techniques for Efficient Electronic System Design, 2013.[42]
- IET Circuits, Devices, & Systems Journal (CDS) on Design Methodologies for Nanoelectronic Digital and Analog Circuits, 2013.[43]
- ACM Journal on Emerging Technologies in Computing Systems (JETC) on New Circuit and Architecture Level Solutions for Multidiscipline Systems, 2012.[44]
- ASP Journal of Low Power Electronics (JOLPE) on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design, 2012.[45]
- Elsevier International Journal on Computers and Electrical Engineering (CEE) on Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia, 2009.[46]
Conference Steering Committee Member
- IEEE-CS Annual Symposium on VLSI (ISVLSI).[47]
- IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS).
- International Conference on Information Technology (ICIT), Orissa Information Technology Society.[48] [49]
Conference General or Program Chair
- 15th IEEE-CS Annual Symposium on VLSI, 2016 (ISVLSI 2016).
- 1st IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS), 2015.[50][51][52]
- 14th IEEE-CS Annual Symposium on VLSI, 2015 (ISVLSI 2015).
- 13th IEEE-CS Annual Symposium on VLSI, 2014 (ISVLSI 2014).
- 13th International Conference on Information Technology, 2014 (ICIT 2014).[53]
- 11th IEEE-CS Annual Symposium on VLSI, 2012 (ISVLSI 2012).
- 9th International Conference on Information Technology, 2006 (ICIT 2006).[54][55]
Notable Talks
- Keynote Address "DfX for Nanoelectronic Embedded Systems" at the International Conference on Control, Automation, Robotics and Embedded System (CARE 2013), IIITDM Jabalpur, India, 2013.
- Invited Talk "Unified Challenges in Nano-CMOS High-Level Synthesis" at the 22nd International Conference on VLSI Design, 2009 (VLSID 2009).[56]
Professional Membership
- Senior Member of Association for Computing Machinery (ACM).
- Senior Member of Institute of Electrical and Electronics Engineers (IEEE).
Honors and Awards
- Chair of Technical Committee on VLSI (TCVLSI), IEEE Computer Society (IEEE-CS).[57]
- Received 2016 PROSE Award for best Textbook in Physical Sciences & Mathematics from the AAP.[58]
- Best Ph.D. Forum Paper Award at the 14th IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2015.[59]
- University of North Texas Provost’s Thank a Teacher recognition in multiple years.
- Honors Day recognition as an inspirational faculty at the University of North Texas in multiple years.
- He has been recognized as a notable alumnus of all his undergraduate and graduate alma maters wherever he studied in India and the USA.[60][61][62][63]
- Government of India Scholarship through Graduate Aptitude Test in Engineering (GATE) in 1997 and 1996 with top 1% all India ranking in Electrical Engineering.
- Awarded Junior Research Fellowship of Council of Scientific and Industrial Research (CSIR), India in 1995.
- Topper of 1995 batch Electrical Engineering of Orissa University of Agriculture and Technology, Bhubaneswar, India, 1995.
- Topper of the 1990 batch of 10+2 class of the Rajdhani College, Bhubaneswar in the Council of Higher Secondary Education, Odisha examination.
- Topper of the 1998 batch of 10 class of the Badagada Government High School, Bhubaneswar in the Board of Secondary Education, Odisha examination.
- In November 1988, he received the President's Scout Award from then President of India, President R. Venkataraman.
- In January 1988, he received the Governor's Scout Award from then Governor of Odisha, Governor Bishambhar Nath Pande.
Patents
Saraju Mohanty is an inventor of 4 US patents which have wide applications in Digital watermarking, Digital rights management (DRM), and Mixed-signal integrated circuit design:[64][65][66]
- Methodology for Nanoscale Technology-based Mixed-Signal System Design.[67]
- Intelligent Metamodel Integrated Verilog-AMS for Fast and Accurate Analog Block Design Exploration.[68]
- Apparatus and Method for Transmitting Secure and/or Copyrighted Digital Video Broadcasting Data Over Internet Protocol Network.[69]
- Methods and Devices for Enrollment and Verification of Biometric Information in Identification Documents.[70]
Books
Saraju Mohanty has authored or edited 6 books which are widely used as text/reference:
- Nanoelectronic Mixed-Signal System Design, McGraw-Hill, 2015, ISBN 978-0071825719.[71] (Received 2016 PROSE Award for best Textbook in Physical Sciences & Mathematics from the AAP.)
- Nano-CMOS and Post-CMOS Electronics: Devices and Modelling, The Institute of Engineering and Technology (IET), 2016, ISBN 1849199973, ISBN 978-1849199971.[72]
- Nano-CMOS and Post-CMOS Electronics: Circuits and Design, The Institute of Engineering and Technology (IET), 2016, ISBN 184919999X, ISBN 978-1849199995.[73]
- Robust SRAM Designs and Analysis, Springer, 2012, ISBN 1461408172.[74]
- Proceedings of 12th International Conference on Information Technology (ICIT), McGraw-Hill, 2009, ISBN 978-0-07-068014-2.
- Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, Springer, 2008, ISBN 0387764739.[75]
Notable Articles for Advancement of Science and Engineering
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Gallery
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Saraju Mohanty was a guest of honor at Ranpur Mahostav 2016 with Member of Odisha Legislative Assembly Rabinarayan Mohapatra, Nayagarh District Magistrate & Collector Hemanta Kumar Padhi, and others.
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Saraju Mohanty as a Conference Chair during lunch at iNIS 2015, Indore with Madhya Pradesh Legislative Assembly Sitasharan Sharma, Chancellor Oriental University Indore K. L. Thakral, Praveen Thakral, and others.
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Saraju Mohanty as a Conference Chair along with the delegates of ISVLSI 2015 at Montpellier, France.
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Saraju Mohanty as a Chair of Technical Committee on VLSI at IEEE Panel of Conference Organizers, 2015, at Glasgow, Scotland.
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Saraju Mohanty as a conference chair inaugurates ICIT 2014 with former director of Indian Institute of Technology Kharagpur Damodar Acharya, the chairman of IEEE Kolkata Section Debatosh Guha, and others in Bhubaneswar, India.
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Saraju Mohanty as CETB Distinguished Alumnus at CETB Campus, Bhubaneswar, India, 2014.
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Saraju Mohanty after delivering an invited talk at College of Engineering and Technology, Bhubaneswar, Bhubaneswar, India, 2014.
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Saraju Mohanty at Energy-Efficient Building Workshop in Tallinn, Estonia, 2013 with Ambassador Vergniaud Elyseu Filho, the Federative Republic of Brazil Ambassador to Estonia, Mayor Mark Burroughs of City of Denton, Texas, USA, Mayor Marcelo Rangel of City of Ponta Grossa, Paraná, Brazil, Madis Saluveer, then Head of Department Of Research Funding, Estonian Research Council, and others.
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Saraju Mohanty delivering an invited talk at energy-efficient building workshop in University of Tartu, Tartu, Estonia in 2013.
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Saraju Mohanty Delivers a Keynote at CARE-2013, Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, Jabalpur, India.
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Saraju Mohanty in a discussion with the enthusiastic researchers at Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, Jabalpur, India, in 2013.
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Saraju Mohanty after an invited talk at Oriental Institute of Science and Technology, Bhopal in 2013 with Chancellor Oriental University Indore K. L. Thakral, Praveen Thakral, and others.
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Saraju Mohanty after an invited talk at the Electrical Engineering Department at IISc, Bangalore in 2010.
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Saraju Mohanty as a Program Chair inaugurates ICIT 2006 with Odisha Governor Rameshwar Thakur in Bhubaneswar, India.
Doctoral Dissertations Supervised
- Geostatistical Inspired Metamodeling and Optimization of Nanoscale Analog Circuits, University of North Texas, Spring 2014.
- Secure and Energy Efficient Execution Frameworks Using Virtualization and Light-Weight Cryptographic Components, University of North Texas, Summer 2014.
- Layout-Accurate Ultra-Fast System Level Design Exploration Through Verilog-AMS, University of North Texas, Spring 2013.
- Metamodeling-Based Fast Optimization of Nanoscale AMS-SoCs, University of North Texas , Spring 2010.
- Process-Voltage-Temperature Aware Nanoscale Circuit Optimization, University of North Texas, Fall 2010.
- Variability Aware Low-Power Techniques for Nanoscale Mixed-Signal Circuits, University of North Texas, Spring 2009.
Education
Prof. Mohanty earned a Ph.D. in Computer engineering from the University of South Florida (USF) in 2003. His Ph.D. mentor at the University of South Florida was Prof. N. Ranganathan (IEEE Fellow and AAAS Fellow).[76]
He received Masters degree in Engineering in Systems Science and Automation (SSA) from the Indian Institute of Science (IISc), Bangalore, India in 1999. His master's thesis mentors at the Indian Institute of Science (IISc), Bangalore were Prof. K. R. Ramakrishnan[77] and Prof. Mohan S. Kankanhalli[78] (IEEE Fellow). He carried out his Master's thesis work at the Multimedia Systems Lab of the Supercomputer Education and Research Centre at Indian Institute of Science.
He received his bachelor's degree (with Honors) in Electrical Engineering (EE) from the College of Engineering and Technology, Bhubaneswar, Orissa University of Agriculture and Technology (OUAT), Bhubaneswar, India in 1995. The College of Engineering and Technology, Bhubaneswar is an institute owned by the Government of Odisha located in the capital city of Bhubaneswar which only admits top-ranked holders of the state Engineering Entrance Examination. He received a number of scholarships throughout his undergraduate and graduate studies.
He completed a 10+2 Science degree from the Rajdhani College, Bhubaneswar in 1990. His high school education from the Badagada Government High School, Bhubaneswar completed in 1988. He was a quite active and recognized member of The Bharat Scouts and Guides.
Personal life
Prof. Mohanty was born in Lodhachua, Ranpur, in the state of Odisha, India near the capital city of Bhubaneswar. He lived in Bhubaneswar until he completed his undergraduate education from College of Engineering and Technology, Bhubaneswar. In 1997, he moved to Bangalore for his Masters studies at Indian Institute of Science (IISc) Bangalore. After completing the Masters education, he moved to USA for his doctoral education. In 2003, he completed his Ph.D. It is during while doing his doctoral studies that he met his wife Dr. Uma Choppali. Dr. Uma Choppali had her Masters in Physics from the Indian Institute of Technology Bombay, India. She was enrolled in Ph.D. (Physics) at the University of South Florida at Tampa, Florida, when they met. They got married in 2003 at Tampa, Florida. Dr. Uma Choppali completed her Ph.D. in Materials Science and Engineering from the University of North Texas at Denton.
References
- ↑ The University of North Texas, Dept. of Computer Science and Engineering, NanoSystem Design Laboratory, http://nsdl.cse.unt.edu/
- ↑ The University of North Texas, Dept. of Computer Science and Engineering, http://www.cse.unt.edu/site/node/91
- ↑ Research Interests, Prof. Saraju Mohanty, http://www.cse.unt.edu/~smohanty/Research.html
- ↑ Dr. Saraju Mohanty Serves as the Chair of the Technical Committee on Very Large Scale Integration (TCVLSI), https://facultysuccess.unt.edu/dr-saraju-mohanty-serves-chair-technical-committee-very-large-scale-integration-tcvlsi
- ↑ Technical Committee on VLSI, http://www.computer.org/portal/web/tandc/tcvlsi
- ↑ ResearchGate - Saraju Mohanty, http://www.researchgate.net/profile/Saraju_Mohanty
- ↑ Google Scholar List - Saraju Mohanty, https://scholar.google.com/scholar?hl=en&q=saraju+mohanty
- ↑ DBLP - Saraju Mohanty, http://dblp.uni-trier.de/pers/hd/m/Mohanty:Saraju_P=.html
- ↑ Interviews: Energy Efficient Buildings & Communities Workshop, University of Tartu, Estonia, http://www.uttv.ee/naita?id=17227&keel=eng
- ↑ Less time on the charger, http://www.unt.edu/features/mohanty/index.htm
- ↑ US Department of Energy, E-print Network, Computer Technologies and Information Sciences, Preprints Provided by Individual Scientists, http://www.osti.gov/eprints/pathways/computertechM.shtml
- ↑ Google Scholar Citation - Saraju P. Mohanty, https://scholar.google.com/citations?user=G0uvNwsAAAAJ&hl=en
- ↑ At one-billionth of a meter, scientists create on the cutting edge, UNT Research Magazine, Volume 20, 2011, http://www.unt.edu/untresearch/2010-2011/advancing-nanotechnology.htm
- ↑ UNT researcher works to make energy-efficient chips, August 20, 2009, https://news.unt.edu/news-releases/unt-researcher-works-make-energy-efficient-chips
- ↑ Rate my Professors, Saraju Mohanty, Professor in the Computer Science department, University of North Texas, Denton, TX, http://www.ratemyprofessors.com/ShowRatings.jsp?tid=1664572
- ↑ DFX for Nanoelectronic Embedded Systems, Keynote Address at First IEEE Sponsored International Conference on Control, Automation, Robotics and Embedded System, CARE-2013, http://care.iiitdmj.ac.in/Keynote_Speakers.html.
- ↑ S. P. Mohanty and E. Kougianos, "Polynomial Metamodel Based Fast Optimization of Nano-CMOS Oscillator Circuits", Analog Integrated Circuits and Signal Processing Journal, Vol. 79, Issue 3, June 2014, pp. 437-453.
- ↑ S. P. Mohanty and E. Kougianos, "Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs", IEEE Transactions on Semiconductor Manufacturing, Vol. 27, Issue 1, February 2014, pp. 22--31.
- ↑ Saraju Mohanty and Elias Kougianos, "Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis", in Proceedings of the 20th International Conference on VLSI Design, pp. 577-582, 2007.
- ↑ S. P. Mohanty, M. Gomathisankaran, and E. Kougianos, "Variability-Aware Architecture Level Optimization Techniques for Robust Nanoscale Chip Design", Elsevier Computers and Electrical Engineering Journal, Vol. 40, Issue 1, January 2014, pp. 168--193.
- ↑ Y. Chen, Y. Wang, A. Takach, Y. Xie. "Parametric Yield Driven Resource Binding in High-Level Synthesis with Multi-Vth Vdd Library and Device Sizing", Journal of Electrical and Computer Engineering, Volume 2012, Article ID 105250, 14 pages, 2012.
- ↑ "Unified Challenges in Nano-CMOS High-Level Synthesis", Invited Talk, 22nd IEEE International Conference on VLSI Design, 2009.
- ↑ Secure digital camera#Secure digital camera
- ↑ Saraju Mohanty, "A Secure Digital Camera Architecture for Integrated Real-Time Digital Rights Management", Elsevier Journal of Systems Architecture, Vol. 55, Issues 10-12, Oct-Dec 2009, pp. 468-480.
- ↑ S. P. Mohanty, O. B. Adamo, and E. Kougianos, "VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera", in Proceedings of the 25th IEEE International Conference on Consumer Electronics, pp. 485-486, 2007.
- ↑ Thomas Winkler, Adam Erdelyi, and Bernhard Rinner, "TrustEYE M4: Protecting the Sensor--not the Camera", in Proceedings of the International Conference on Advanced Video and Signal Based Surveillance, 2014.
- ↑ S. D. Roy, Xin Li, Y. Shoshan, A. Fish, and O. Yadid-Pecht, "Hardware Implementation of a Digital Watermarking System for Video Authentication", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 23, Issue 2, 2013, pp. 289-301.
- ↑ C. -T. Yen, T. -C. Wu, M. -H. Guo, C. -K. Yang, and H. -C. Chao, "Digital product transaction mechanism for electronic auction environment", IET Information Security, Vol. 4, Issue 4, 2010, pp. 248–257.
- ↑ S. P. Mohanty, N. Ranganathan, and R. K. Namballa, "VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder", in Proceedings of the IEEE Workshop on Signal Processing System, pp. 183-188, 2003.
- ↑ S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, "Design of a Low Power Image Watermarking Encoder using Dual Voltage and Frequency", in Proceedings of the 18th IEEE International Conference on VLSI Design, pp. 153-158, 2005.
- ↑ IEEE Consumer Electronics Magazine (MCE) -- IEEE Consumer Electronics Magazine Editorial Board Member Roster, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7308143
- ↑ VLSI Circuits and Systems Letter (VCAL) -- Editorial Board, http://www.tcvlsi.org/vlsi-circuits-and-systems-letter/
- ↑ IET Circuits, Devices and Systems (CDS) -- Editorial board, http://digital-library.theiet.org/journals/iet-cds/editorial-board
- ↑ Integration, the VLSI Journal -- Editorial Board, http://www.journals.elsevier.com/integration-the-vlsi-journal/editorial-board/
- ↑ ASP Journal of Low Power Electronics (JOLPE) -- Editorial Board, http://www.aspbs.com/jolpe/editorial_jolpe.htm
- ↑ Special Issue on Circuit and System Design Automation for Internet of Things, https://mc.manuscriptcentral.com/societyimages/tcad/CFP_Special-Circuit%20and%20System%20Design%20Automation%20for%20Internet%20of%20Things.pdf
- ↑ IEEE Transactions on Nanotechnology (TNANO) -- Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing, http://sites.ieee.org/tnano/2015/12/special-issue-ion-processing/
- ↑ ACM Journal on Emerging Technologies in Computing Systems (JETC) -- Nanoelectronic Circuit and System Design Methods for Mobile Computing Era, http://jetc.acm.org/pdf/ACM-JETC_SI_NanoMobi_CFP.pdf
- ↑ Elsevier The VLSI Integration Journal (Integration) -- Hardware Assisted Techniques for IoT and Bigdata Applications, http://www.journals.elsevier.com/integration-the-vlsi-journal/call-for-papers/special-issue-on-hardware-assisted-techniques-for-iot/
- ↑ IEEE Access -- Security and Reliability Aware System Design for Mobile Computing Systems, http://www.ieee.org/publications_standards/publications/ieee_access/security_reliability.pdf
- ↑ IEEE Transactions on Emerging Topics in Computing (TETC) -- Circuit and System Design Methodologies for Emerging Technologies, Vol. 3, No. 4, October–December 2015, http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6245516
- ↑ Springer Circuits, Systems, and Signal Processing Journal (CSSP), Volume 32, Issue 6, December 2013, http://link.springer.com/journal/34/32/6/page/1
- ↑ IET Circuits, Devices, & Systems Journal (CDS), Volume 7, issue 5, September 2013, http://digital-library.theiet.org/content/journals/iet-cds/7/5#headline1
- ↑ ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 8, Issue 3, August 2012, http://portalparts.acm.org/2290000/2287696/fm/frontmatter.pdf?ip=173.74.56.32&CFID=735311818&CFTOKEN=90085137
- ↑ ASP Journal of Low Power Electronics (JOLPE), Volume 8, Issue 3, June 2012, http://www.aspbs.com/jolpe/contents_jolpe2012.htm#v8n3
- ↑ Elsevier International Journal on Computers and Electrical Engineering, Volume 35, Issue 2, March 2009, http://www.sciencedirect.com/science/journal/00457906/35/2
- ↑ IEEE Computer Society Annual Symposium on VLSI (ISVLSI), http://www.isvlsi.org
- ↑ International Conference on Information Technology (ICIT), http://www.oits-icit.org
- ↑ Orissa Information Technology Society, http://www.oits.org
- ↑ International Symposium on Nanoelectronic and Information Systems (IEEE iNIS 2015), 21–23 December 2015, Indore, India, http://www.globaleventslist.elsevier.com/events/2015/12/international-symposium-on-nanoelectronic-and-information-systems-inis/
- ↑ Computer Science and Engineering Researcher Chairs International Symposium, August 2015, http://engineering.unt.edu/computer-science-and-engineering-researcher-chairs-international-symposium
- ↑ IEEE’s first intl symposium on iNIS to be held in City, Aug 17, 2015, http://www.freepressjournal.in/ieees-first-intl-symposium-on-inis-to-be-held-in-city/
- ↑ A student research symposium was organised by ISTE-Silicon Student chapter - See more at: http://www.orissadiary.com/CurrentNews.asp?id=56591#sthash.iP2IFtmy.dpuf
- ↑ The International Conference on Information Technology (ICIT), http://www.oits-icit.org
- ↑ Orissa Information Technology Society (OITS), http://www.oits.org/
- ↑ The 22nd International Conference on VLSI Design -- Unified Challenges in Nano-CMOS High-Level Synthesis, 2009, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4749726&newsearch=true&queryText=Unified%20Challenges%20in%20Nano-CMOS%20High-Level%20Synthesis
- ↑ Technical & Conferences Activities Board -- Technical Committees -- Technical Committee on VLSI, http://www.computer.org/web/tandc/tcvlsi
- ↑ 2016 PROSE Award Winners, https://proseawards.com/winners/2016-award-winners/#body
- ↑ ISVLSI 2015, http://www.eng.ucy.ac.cy/theocharides/isvlsi15/
- ↑ USF Notable Alumnus, Bulls to Brag About, USF Alumni Association Website.
- ↑ Indian Institute of Science Notable Alumnus, Indian Institute of Science.
- ↑ College of Engineering and Technology, Bhubaneswar Notable Alumnus, College of Engineering and Technology, Bhubaneswar
- ↑ CET Rising, Interviewed: Mr. Saraju Mohanty, Interview Taken by: Trishala Mishra, Saturday, 29 August 2015, http://rising.cetb.in/2015/08/interviewed-mr-saraju-mohanty.html
- ↑ Engineering Professors Awarded Multiple Patents to Innovate Integrated Circuit Design, UNT Faculty Success Newsletter, October 2015, https://facultysuccess.unt.edu/unt-faculty-newsletter-october-2015-edition.
- ↑ Researchers Receive Patent for a Method for Designing Complex, Mixed-signal Circuits, October 2015, http://engineering.unt.edu/researchers-receive-patent-method-designing-complex-mixed-signal-circuits
- ↑ Researchers Awarded Patent for Method to Innovate Mixed-signal Integrated Circuit Design, May 2015, http://engineering.unt.edu/researchers-awarded-patent-method-innovate-mixed-signal-integrated-circuit-design
- ↑ Methodology for Nanoscale Technology based Mixed-Signal System Design, US Patent Number: 9,053,276, Issued on: 9th June 2015 http://assignment.uspto.gov/#/assignment?id=30967-123&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
- ↑ Intelligent Metamodel Integrated Verilog-AMS for Fast and Accurate Analog Block Design Exploration, US Patent Number: 9,026,964, Issued on: 5th May 2015 http://assignment.uspto.gov/#/assignment?id=32972-875&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
- ↑ Apparatus and Method for Transmitting Secure and/or Copyrighted Digital Video Broadcasting Data Over Internet Protocol Network, US Patent Number: 8,423,778, Issued on: 16th Apr 2013 http://assignment.uspto.gov/#/assignment?id=22252-43&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
- ↑ Methods and Devices for Enrollment and Verification of Biometric Information in Identification Documents, US Patent Number: 8,058,972, Issued on: 15th Nov 2011 http://assignment.uspto.gov/#/assignment?id=21372-691&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
- ↑ http://www.mhprofessional.com/product.php?isbn=0071825711
- ↑ http://www.theiet.org/resources/books/circuits/nano-cmos-post-cmos-vol1.cfm
- ↑ http://www.theiet.org/resources/books/circuits/Ncmosvol2.cfm
- ↑ http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4614-08178
- ↑ http://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-76473-3
- ↑ Prof. Nagarajan "Ranga" Ranganathan, Ph.D. Distinguished University Professor, http://cans.cse.usf.edu/faculty/ranga/
- ↑ K. R. Ramakrishnan, Professor, Department of Electrical Engineering, Indian Institute of Science, http://www.ee.iisc.ernet.in/new/people/faculty/krr/index.html
- ↑ Mohan S. Kankanhalli, Vice Provost (Graduate Education), National University of Singapore, Professor, Department of Computer Science, School of Computing, http://www.comp.nus.edu.sg/~mohan/