RISC-V

RISC-V
Designer UC Berkeley
Bits 32, 64, 128
Introduced 2010
Version 2.0
Design RISC
Type Load-store
Encoding Variable
Branching Compare-and-branch
Endianness Little
Extensions M, A, F, D, C
Open Yes
Registers
General purpose 16, 32 (x0=0)
Floating point 32
Prototype of a RISC-V processor, January 2013

RISC-V (pronounced "risk-five") is an open source instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.

In contrast to most ISAs, RISC-V is freely available for all types of use, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Such uses demand that the designers consider both performance and power efficiency. The instruction set also has a substantial body of supporting software, which fixes the usual weakness of new instruction sets.

The project was originated in 2010 by researchers in the Computer Science Division at UC Berkeley, but many contributors are volunteers and industry workers that are unaffiliated with the university.[1]

The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind,[2][3] but without "over-architecting" for a particular microarchitecture style.[3][4][5][6]

As of 2014 version 2 of the userspace ISA is fixed.[7]

Significance

The RISC-V authors aim to provide several freely available CPU designs, under a BSD license. This license allows derivative works such as RISC-V chip designs to be either open and free like RISC-V itself, or closed and proprietary, (unlike the available OpenRISC cores, which under the GPL, requires that all derivative works also be open and free).

By contrast, commercial chip vendors such as ARM Holdings and MIPS Technologies charge substantial license fees for the use of their patents.[8] They also require non-disclosure agreements before releasing documents that describe their designs' advantages and instruction set. Many design advances are completely proprietary, never described even to customers. The secrecy interferes with legitimate public educational use, security auditing, and the development of public, inexpensive open-source free software compilers and operating systems.

Developing a CPU requires expertise in several specialties: Logic design, compiler design and operating system design. It's rare to find this outside of a professional engineering team. The result is that modern, high-quality general-purpose computer instruction sets have not recently been widely available anywhere or even explained except in academic settings. Because of this, many RISC-V contributors see it as a unified community effort. This need for a large base of contributors is part of the reason why RISC-V was engineered to fit so many uses.

The RISC-V authors also have substantial research and user-experience validating their designs in silicon and simulation. The RISC-V ISA is a direct development from a series of academic computer-design projects and was originated in part to aid such projects.[3][9]

History

Predecessors

RISC designs labelled as such date from about 1980 and have always been of academic interest.[10]

Academics created the RISC instruction set DLX for use in the first edition of the textbook Computer Architecture: A Quantitative Approach in 1990. However it was intended primarily for educational use. Academics and hobbyists implemented it using field-programmable gate-arrays, but it was not a commercial success.

ARM CPUs, version 2 and earlier, had a public-domain instruction set, and it is still supported by GCC, a popular free software compiler. This helped promote acceptance of the ARM architecture. Three open-source cores exist for this ISA, but they have not been manufactured.[11][12]

OpenRISC is an open-source ISA with associated RISC designs that is based on DLX. It is fully supported with GCC and Linux implementations. However, it does not have many commercial implementations.

Foundation

Krste Asanovic at UC Berkeley, who found many uses for an open-source computer system, decided to develop and publish one to help both academic and industrial users.[9] This effort was aided by David Patterson, one of the authors of the seminal paper on RISC,[10] who is a prominent UC Berkeley professor.

Design

RISC-V has 32 integer registers and, optionally, 32 floating-point registers. Very small RISC-V integer CPUs may have 16 registers. Memory is addressed as 8-bit bytes. Register number 0 is a constant 0. The assembler uses register 0 as a placeholder to make any of several human-readable instructions into one machine instruction. (E.g. "move rx to ry" becomes "add r0 to rx and store in ry.")[3]

Like many RISC designs, it is a "load-store" machine. The only instructions that access main memory are loads and stores. All arithmetic and logic operations occur between registers.[3]

Unlike other academic designs which are optimized for simplicity of exposition, the RISC-V instruction set is designed for practicality of implementation, with features to increase a computer's speed, while reducing its cost and power usage. These include placing most-significant bits at a fixed location to speed sign-extension, and a bit-arrangement designed to reduce the number of multiplexers in a CPU.[3] The designers claim that RISC-V CPUs can achieve higher speeds, lower power and smaller, less-expensive electronics than some comparable commercial CPUs.[2]

The standard RISC-V ISA specifies that all instructions are 32 bits. This makes for a particularly simple implementation, but a program's code is larger than in many other instruction sets.[3][13] To compensate, RISC-V reserves opcode space for a variable-length instruction set.[3][13] The smaller, 16-bit subset is called RISC-V Compressed.[3] A prototype includes 33 of the most frequently-used instructions, recoded into a more-compact 16-bit format.[13] The researchers intend to reduce the code's binary size, power and cost for small computers, especially embedded computer systems. A prototype of RISC-V Compressed has been tested.[13] Research with the prototype showed that the code was 20% smaller than an x86 PC and the MIPS' compressed code, and 2% larger than ARM's Thumb-2 code.[13] Unlike Thumb, there is no separate operating mode; standard and compressed instructions may be freely intermixed. The smaller code reduces a RISC-V computer's memory, cache memory and power demands.[13]

RISC-V intentionally lacks condition codes, and even lacks a carry bit.[3] The designers claim that this can simplify CPU designs by minimizing interactions between instructions.[3] Instead RISC-V builds comparison operations into its conditional-jumps.[3] Use of comparisons may slightly increase its power usage in some applications. The lack of a carry bit complicates multiple-precision arithmetic. RISC-V does not detect or flag most arithmetic errors, including overflow, underflow and divide by zero.[3] RISC-V also lacks the "count leading zero" and bit-field operations normally used to speed software floating-point in a pure-integer processor.

Many RISC designs included a branch delay slot, a position after a branch instruction that can be filled with an instruction which is executed regardless of whether the branch is taken or not. This feature can improve performance of processors that have five pipeline stages, but it was omitted because it complicates multicycle CPUs, superscalar CPUs, and CPUs with pipelines longer than five stages.The success of dynamic branch predictors reduces the need for delayed branches.[3]

Like most RISC CPUs, RISC-V lacks address-modes that "write back" to the registers. For example, it does not do auto-incrementing. A load or store can add a twelve-bit signed offset to a register that contains an address. A further 20 bits (yielding a 32-bit address) can be generated at an absolute address.[3]

RISC-V was designed to permit position-independent code. It has a special instruction to generate 20 upper address bits that are relative to the program counter. The lower twelve bits are provided by normal loads, stores and jumps.[3]

The RISC-V instruction set was designed for research, and therefore includes extra space for new instructions. Planned instruction subsets include system instructions, atomic access, integer multiplication, floating-point arithmetic, bit-manipulation, decimal floating-point, multimedia and vector processing. It includes instructions for 32-bit, 64-bit and 128-bit integer and floating-point. It was designed for 32-bit, 64-bit and 128-bit memory systems, with 32-bit models designed for lower power, 64-bit for higher performance, and 128-bit for future requirements. It's designed to operate with hypervisors, supporting virtualization. It was designed to conform to recent floating-point standards.[3]

RISC-V can load and store 8 and 16-bit items, but it lacks 8 and 16-bit arithmetic, including comparison-and-branch instructions.[3] The 64-bit instruction set includes 32-bit arithmetic.[3] There is a proposal to use the floating-point registers to perform parallel sub-word arithmetic for multimedia.[3]

RISC-V does define a special set of integer multiplication instructions. This includes a recommended sequence of instructions that a compiler can generate and a CPU can interpret to perform a fused multiply-accumulate operation. Multiply-accumulate is a core primitive of numerical linear algebra, and so is incorporated as part of a common benchmark, Coremark.[3][14]

Vector extension

The planned multimedia set is currently a general-purpose mixed-precision vector processor similar to the research project "Hwacha."[3][15] (The name is a play on the code name "rocket" of a RISC-V prototype; a hwacha is a historical multiple rocket launcher.)

Unlike the short-vector SIMD extensions used in x86 and ARM processors which force an architectural change to expand the vector registers (in the case of x86, from 64-bit MMX registers to 128-bit SSE, to 256-bit AVX, and AVX-512), the RISC-V proposal is a more Cray-like long-vector design.

Rather than fix the vector length in the architecture, an instruction (setvl) is available which takes a requested size and sets the vector length to the minimum of the hardware limit and the requested size.

Taking advantage of this flexibility, the vector length is not only architecturally variable, but designed to vary at run time as well. Unlike fixed-length SIMD registers where the number of entries depends on the size of each entry, each vector is the same length.

The application specifies the total vector width it requires, and the processor determines the vector length it can provide with available on-chip resources. This takes the form of an instruction (vsetcfg) with four immediate operands, specifying the number of vector registers of each available width required. The total must be no more than the addressable limit of 32, but may be less if the application does not require them all. The vector length is limited by the available on-chip storage divided by the number of bytes of storage required for each entry. (There may be additional hardware limits as well.)

Outside of vector loops, the application can request zero vector registers, saving the operating system the trouble of preserving them on context switches

External Debug System

There is a preliminary specification for RISC-V's hardware-assisted debugger.[16] It will use a transport system such as JTAG or USB to access the system bus. All RISC-V registers and I/O devices are to be made available on the system bus. This gives the debugger access to debug hardware, CPU registers and even I/O devices. Standard debug hardware should include a debug module, and optional modules for hardware trace and breakpoints. A small ROM (for debug code and tables describing the system) should also be available. A similar system has worked well for the OpenRISC project.[17]

Software

The RISC-V website has a specification for user-mode instructions. It also includes the files of six CPU designs, the 64-bit "Rocket" and five "Sodor" CPUs. The software includes a design compiler, Chisel,('"Constructing Hardware in a Scala Embedded Language"')[18] which is able to reduce the designs to Verilog for use in devices. The website includes verification data for testing core implementations. Available RISC-V software includes a GNU Compiler Collection (GCC) toolchain (with GDB, the debugger), an LLVM toolchain, a simulator ("Spike") and the standard simulator QEMU.

Operating systems support exists for Linux, FreeBSD and NetBSD, but the supervisor-mode instructions are not standardized at this time, so this support is provisional (as of September 25, 2014). The preliminary FreeBSD port to the RISC-V architecture was upstreamed in February 2016, and will ship in FreeBSD 11.0.[19][20] There is also a simulator to run a RISC-V Linux system on a web browser using JavaScript.

Adopters

Similar projects

References

  1. ↑ "Contributors". riscv.org. Regents of the University of California. Retrieved August 25, 2014.
  2. 1 2 "Rocket Core Generator". RISC-V. Regents of the University of California. Retrieved 1 October 2014.
  3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Waterman, Andrew, et. al. "The RISC-V Instruction Set Manual Vol. I, User-Level ISA, version 2.0". RISC-V Downloads. Regents of the University of California. Retrieved 2014-08-25.
  4. ↑ Celio, Christopher; Love, Eric. "ucb-bar/riscv-sodor". GitHub Inc. Regents of the University of California. Retrieved 12 February 2015.
  5. 1 2 "SHAKTI Processor Project". Indian Institute of Technology Madras. Retrieved September 15, 2014.
  6. ↑ Celio, Christopher. "CS 152 Laboratory Exercise 3" (PDF). UC Berkeley. Regents of the University of California. Retrieved 12 February 2015.
  7. ↑ Waterman, Andrew; Lee, Yunsup; Patterson, David A.; Asanovi, Krste. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2 (Technical Report EECS-2014-54)". University of California, Berkeley. Retrieved December 26, 2014.
  8. ↑ Demerjian, C. (2013). “A long look at how ARM licenses chips: Part 1” semiaccurate.com/2013/08/07/a-long-look-at-how-arm-licenses-chips, “How ARM licenses it’s IP for production: Part 2” semiaccurate.com/2013/08/08/how-arm-licenses-its-ip-for-production
  9. 1 2 Asanovic, Krste. "Instruction Sets Should be Free: The Case for RISC-V". RISC-V. Regents of the University of California. Retrieved 2014-08-25.
  10. 1 2 Patterson, David A; Ditzel, David R. (October 1980). "The Case for the Reduced Instruction Set Computer". ACM SIGARCH Computer Architecture News 8 (6): 25. Retrieved August 25, 2014.
  11. ↑ "Amber ARM-compatible core". OpenCores. OpenCores. Retrieved 26 August 2014.
  12. ↑ "ARM4U". OpenCores. OpenCores. Retrieved 26 August 2014.
  13. 1 2 3 4 5 6 Waterman, Andrew (May 13, 2011). Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed. U.C. Berkeley: Regents of the University of California. p. 32. Retrieved 2014-08-25.
  14. ↑ "Coremark FAQ, "What factors are involved in improving a device?"". Coremark, an EEMBC Benchmark. EEMBC. Retrieved 1 October 2014.
  15. ↑ Ou, Albert; et al. "A Case for MVPs: Mixed-Precision Vector Processors" (PDF). prism.sejong.ac.kr. Retrieved 1 October 2014.
  16. ↑ Newsome, Tim. "RISC-V External Debug" (PDF). RISC-V. The Regents of the University of California. Retrieved 11 February 2016.
  17. ↑ Anonymous. "Debugging Physical Targets - OR1K". Open Cores. ORSoC AB. Retrieved 11 February 2016.
  18. ↑ "Chisel: Constructing Hardware in a Scala Embedded Language". UC Berkeley. Regents of the University of California. Retrieved 12 February 2015.
  19. ↑ "FreeBSD Wiki: RISC-V".
  20. 1 2 "FreeBSD Foundation: Initial FreeBSD RISC-V Architecture Port Committed".
  21. ↑ Merritt, Rick. "Google, Oracle and HP Join RISC-V". EE Times. UBM. Retrieved 11 February 2016.
  22. ↑ "IIT Madras Open Source Processor Project". Rapid IO. IIT Madras. Retrieved September 13, 2014.
  23. ↑ "lowRISC website". Retrieved May 10, 2015.
  24. ↑ Oloffsson, Andreas. "Why I will be using RISC-V in my next chip.". Adapteva Blog. Adapteva. Retrieved 11 February 2016.

Further reading

External links

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