Quasi Delay Insensitive
In digital logic design, Quasi Delay-Insensitive (QDI) circuits are a class of almost delay-insensitive asynchronous circuits which are invariant to (and make no assumptions about) the delays of any of the circuit's wires or elements, except to assume that certain fanouts are isochronic. Isochronic forks allow signals to reach two destinations with negligible difference in delay. [1]
More importantly, QDI circuits are Turing-complete, while purely delay-insensitive circuits are not. Of all "useful" asynchronous design styles, QDI circuits make the fewest timing assumptions, as only the isochronic fork is assumed. In practice ensuring the correctness of an isochronic fork is trivial.
Two common design styles of QDI circuits are Delay Insensitive Minterm Synthesis (DIMS) and Pre-Charge Half Buffers based circuits.
Technically, QDI circuits are the same class of circuits as speed-independent circuits. The main difference between speed-independent and QDI circuits is that in QDI circuits, the designer is concerned with the acknowledgment of each transition, whereas in speed-independent design, the correctness of the isochronic assumption on each circuit node is assumed to be true and no distinction is made between circuit nodes that are isochronic forks and those that are not.
Manufactured QDI processor designs include: TITAC from Tokyo Institute of Technology, MiniMIPS from Caltech, SPA from The University of Manchester and ASPRO-216 from France Telecom. The first QDI processor was the Caltech asynchronous microprocessor of 1989 (a predecessor to the MiniMIPS processor).
Isochronic fork
An isochronic fork is a concept in asynchronous digital design. Isochronic forks are forks in wires where if the acknowledging target has seen a transition on their end of the fork then the transition is assumed to have also happened on the other end of the fork too. There are two types of isochronic forks; the asymmetric types only ensure that the signal will reach the acknowledging fork tip before, or at the same time as, it will at the other fork tip, while the symmetric type ensures that both fork tips will be reached at the same time. Symmetrical isochronic forks allow either of the targets to acknowledge the signal. In quasi delay-insensitive (QDI) circuits all forks have to be either isochronic and acknowledged by one of the destinations, or acknowledged by all destinations. The concept of isochronic fork was introduced by A. J. Martin exactly to distinguish between asynchronous circuits that satisfy QDI requirements and those that do not. Martin also established that given reasonable assumptions on the kinds of circuit elements that are available to design with, it is impossible to design interesting systems without including at least some asynchronic forks. Isochronic forks are in some sense the weakest compromise away from fully delay-insensitive systems.
References
- ↑ Scott Hauck (1995). "Asynchronous Design Methodologies: An Overview". PROCEEDINGS OF THE IEEE. pp. 69–93.
- Martin, Alain J. (1990). "The Limitations to Delay-Insensitivity in Asynchronous Circuits". Sixth MIT Conference on Advanced Research in VLSI (MIT Press).