Quad Data Rate SRAM

Quad Data Rate (QDR) SRAM is a type of static RAM computer memory that can transfer up to four words of data in each clock cycle. Like Double Data-Rate (DDR) SDRAM, QDR SRAM transfers data on both rising and falling edges of the clock signal. The main purpose of this capability is to enable reads and writes to occur at high clock frequencies without the loss of bandwidth due to bus-turnaround cycles incurred in DDR SRAM. QDR SRAM uses two clocks, one for read data and one for write data and has separate read and write data buses (also known as Separate I/O), whereas DDR SRAM uses a single clock and has a single common data bus used for both reads and writes (also known as Common I/O). This helps to eliminate problems caused by the propagation delay of the clock wiring, and allows the illusion of concurrent reads and writes (as seen on the bus, although internally the memory still has a conventional single port - operations are pipelined but sequential). When all data I/O signals are accounted, QDR SRAM is not 2x faster than DDR SRAM but is 100% efficient when reads and writes are interleaved. In contrast, DDR SRAM is most efficient when only one request type is continually repeated, e.g. only read cycles. When write cycles are interleaved with read cycles, one or more cycles are lost for bus turnaround to avoid data contention, hence bus efficiency is reduced. Most SRAM manufacturers constructed QDR and DDR SRAM using the same physical silicon, differentiated by a post-manufacturing selection (e.g. blowing a fuse on chip).

QDR SRAM was designed for high-speed communications and networking applications, where data throughput is more important than cost, power efficiency or density. The technology was created by Micron and Cypress, later followed by IDT, then NEC, Samsung and Renesas. Quad Data Rate II+ Memory is currently being designed by Cypress Semiconductor for Radiation Hardened Environments. The device has Total Dose rating of 300Krad, No Latchup at 120 LET and SEU data of 1.34E-10, by using simple SECDED Hamming code.

I/O

Clock inputs

4 clock lines:

• Input clock:
  • K
  • not-K, or /K
• Output clock:
  • C
  • not-C, or /C

Control inputs

Two control lines:

• not-Write enable: /WPS
• not-Read enable: /RPS

Buses

One address bus and two data buses:

• Address bus
• Data in bus
• Data out bus

Clocking scheme

• Addresses
  • Read address latched on rising edge of C
  • Write address latched on rising edge of K (in burst-of-4 mode, burst-of-2 uses rising edge of not-K)

• Data
  • Write
    • If /WPS is low
      • A data word on Data In is latched on rising edge of K
      • The next data word on Data In is latched on rising edge of /K
  • Read
    • A read is a two-cycle process
    • If /RPS is low
      • The first rising edge of C latches the read address, A
      • The second rising edge of C puts the data word, from address A, on the Data Out bus
      • The next rising edge of /C puts the next data word, from address A+1, on the Data Out bus

External links

• Official QDR website QDR web site
• AN4065 QDR-II, QDR-II+, DDR-II, DDR-II+ Design GUide