Pin grid array

Close up to the pins of a pin grid array

The pin grid array at the bottom of a XC68020, a prototype of the Motorola 68020 microprocessor

The pin grid array on the bottom of an AMD Phenom X4 9750 processor that uses the AMD AM2+ socket.

A pin grid array, often abbreviated PGA, is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package.

PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages such as dual in-line package (DIP).

PGA variants

Plastic

The topside of a Celeron-400 in a PPGA packing

Plastic pin grid array (PPGA) packaging was used by Intel for late model Mendocino core Celeron processors based on Socket 370. Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.

Underside of a Pentium 4 in a PGA package

Flip chip

The underside of a FC-PGA package (the die is on the other side)

A flip-chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the heatsink or other cooling mechanism.

The FC-PGA was introduced by Intel with the Coppermine core Pentium III and Celeron^[1] processors based on Socket 370, and was later used for Socket 478-based Pentium 4^[2] and Celeron processors. FC-PGA processors fit into zero insertion force (ZIF) Socket 370 and Socket 478-based motherboard sockets; similar packages have also been used by AMD. It is still used today for mobile Intel processors.

Staggered pin

The Staggered pin grid array (SPGA) is used by Intel processors based on Socket 5 and Socket 7. Socket 8 used a partial SPGA layout on half the processor.

An example of a socket for a staggered pin grid array package.

View of the socket 7 321-pin connectors of a CPU

It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square lattice. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as microprocessors.

Ceramic

A ceramic pin grid array (CPGA) is a type of packaging used by integrated circuits. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some CPUs that use CPGA packaging are the AMD Socket A Athlons and the Duron.

A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on Socket AM2 and Socket AM2+. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a ceramic substrate with pins arranged in an array.

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  A 1.2 GHz VIA C3 microprocessor in a ceramic package

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  133 MHz Pentium chip in a ceramic package

Organic

An organic pin grid array (OPGA) is a type of connection for integrated circuits, and especially CPUs, where the silicon die is attached to a plate made out of an organic plastic which is pierced by an array of pins which make the requisite connections to the socket.

The organic pin grid array was originally introduced for the AMD Athlon XP processors based on Socket A, also used for AMD processors using Socket 754, Socket 939, Socket 940, Socket AM2, and Socket AM2+.

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  The underside of a Celeron-400 in a PPGA

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  An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat sink.

Stud

A Stud Grid Array (SGA) is a short-pinned pin grid array chip scale package for use in Surface-mount technology. The Polymer Stud Grid Array or Plastic Stud Grid Array was developed jointly by the Interuniversity Microelectronics Centre (IMEC) and Laboratory for Production Technology, Siemens AG.^[3][4]

See also

References

• Thomas, Andrew (August 4, 2010). "What the Hell is… a flip-chip?". The Register. Retrieved December 30, 2011.  External link in |publisher= (help)
• "XSERIES 335 XEON DP-2.4G 512 MB". CNET. October 26, 2002. Retrieved December 30, 2011.  External link in |publisher= (help)
• "SURFACE MOUNT NOMENCLATURE AND PACKAGING" (PDF). 

External links

• Intel CPU Processor Identification
• Ball Grid Arrays: the High-Pincount Workhorses, John Baliga, Associate Editor, Semiconductor International, 9/1/1999
• Spot on component packaging, 08/1998, Elektronik, Produktion & Prüftechnik
• Terminology