Canonical normal form

In Boolean algebra, any Boolean function can be put into the canonical disjunctive normal form (CDNF) or minterm canonical form and its dual canonical conjunctive normal form (CCNF) or maxterm canonical form. Other canonical forms include the complete sum of prime implicants or Blake canonical form (and its dual), and the algebraic normal form (also called Zhegalkin or Reed–Muller).

Minterms are called products because they are the logical AND of a set of variables, and maxterms are called sums because they are the logical OR of a set of variables. These concepts are dual because of their complementary-symmetry relationship as expressed by De Morgan's laws.

Two dual canonical forms of any Boolean function are a "sum of minterms" and a "product of maxterms." The term "Sum of Products" or "SoP" is widely used for the canonical form that is a disjunction (OR) of minterms. Its De Morgan dual is a "Product of Sums" or "PoS" for the canonical form that is a conjunction (AND) of maxterms. These forms can be useful for the simplification of these functions, which is of great importance in the optimization of Boolean formulas in general and digital circuits in particular.

Summary

One application of Boolean algebra is digital circuit design. The goal may be to minimize the number of gates, to minimize the settling time, etc.

There are sixteen possible functions of two variables, but in digital logic hardware, the simplest gate circuits implement only four of them: conjunction (AND), disjunction (inclusive OR), and the respective complements of those (NAND and NOR).

Most gate circuits accept more than 2 input variables; for example, the spaceborne Apollo Guidance Computer, which pioneered the application of integrated circuits in the 1960s, was built with only one type of gate, a 3-input NOR, whose output is true only when all 3 inputs are false.[1]

Minterms

For a boolean function of n variables {x_1,\dots,x_n}, a product term in which each of the n variables appears once (in either its complemented or uncomplemented form) is called a minterm. Thus, a minterm is a logical expression of n variables that employs only the complement operator and the conjunction operator.

For example, abc, ab'c and abc' are 3 examples of the 8 minterms for a Boolean function of the three variables a, b, and c. The customary reading of the last of these is a AND b AND NOT-c.

There are 2n minterms of n variables, since a variable in the minterm expression can be in either its direct or its complemented form—two choices per variable.

Indexing minterms

Minterms are often numbered by a binary encoding of the complementation pattern of the variables, where the variables are written in a standard order, usually alphabetical. This convention assigns the value 1 to the direct form (x_i) and 0 to the complemented form (x'_i); the minterm is then \sum\limits_{i=1}^n2^i\operatorname{value}(x_i). For example, minterm a b c' is numbered 1102 = 610 and denoted m_6.

Functional equivalence

A given minterm n gives a true value (i.e., 1) for just one combination of the input variables. For example, minterm 5, a b' c, is true only when a and c both are true and b is false—the input arrangement where a = 1, b = 0, c = 1 results in 1.

Given the truth table of a logical function, it is possible to write the function as a "sum of products". This is a special form of disjunctive normal form. For example, if given the truth table for the arithmetic sum bit u of one bit position's logic of an adder circuit, as a function of x and y from the addends and the carry in, ci:

ci x y u(ci,x,y)
0000
0011
0101
0110
1001
1010
1100
1111

Observing that the rows that have an output of 1 are the 2nd, 3rd, 5th, and 8th, we can write u as a sum of minterms m_1, m_2, m_4, and m_7. If we wish to verify this: u(ci,x,y) = m_1 + m_2 + m_4 + m_7 = (ci',x',y)+(ci',x,y') + (ci,x',y')+(ci,x,y) evaluated for all 8 combinations of the three variables will match the table.

Maxterms

For a boolean function of n variables {x_1,\dots,x_n}, a sum term in which each of the n variables appears once (in either its complemented or uncomplemented form) is called a maxterm. Thus, a maxterm is a logical expression of n variables that employs only the complement operator and the disjunction operator. Maxterms are a dual of the minterm idea (i.e., exhibiting a complementary symmetry in all respects). Instead of using ANDs and complements, we use ORs and complements and proceed similarly.

For example, the following are two of the eight maxterms of three variables:

a + b' + c
a' + b + c

There are again 2n maxterms of n variables, since a variable in the maxterm expression can also be in either its direct or its complemented form—two choices per variable.

Indexing maxterms

Each maxterm is assigned an index based on the opposite conventional binary encoding used for minterms. The maxterm convention assigns the value 0 to the direct form (x_i) and 1 to the complemented form (x'_i). For example, we assign the index 6 to the maxterm a' + b' + c (110) and denote that maxterm as M6. Similarly M0 of these three variables is a + b + c (000) and M7 is a' + b' + c' (111).

Functional equivalence

It is apparent that maxterm n gives a false value (i.e., 0) for just one combination of the input variables. For example, maxterm 5, a' + b + c', is false only when a and c both are true and b is false—the input arrangement where a = 1, b = 0, c = 1 results in 0.

If one is given a truth table of a logical function, it is possible to write the function as a "product of sums". This is a special form of conjunctive normal form. For example, if given the truth table for the carry-out bit co of one bit position's logic of an adder circuit, as a function of x and y from the addends and the carry in, ci:

ci x y co(ci,x,y)
0000
0010
0100
0111
1000
1011
1101
1111

Observing that the rows that have an output of 0 are the 1st, 2nd, 3rd, and 5th, we can write co as a product of maxterms M_0, M_1, M_2 and M_4. If we wish to verify this: co(ci, x, y) = M_0 M_1 M_2 M_4 = (ci + x + y) (ci + x + y') (ci + x' + y) (ci' + x + y) evaluated for all 8 combinations of the three variables will match the table.

Dualization

The complement of a minterm is the respective maxterm. This can be easily verified by using de Morgan's law. For example: M_5 = a' + b + c' = (a b' c)' = m_5'

Non-canonical PoS and SoP forms

It is often the case that the canonical minterm form can be simplified to an equivalent SoP form. This simplified form would still consist of a sum of product terms. However, in the simplified form, it is possible to have fewer product terms and/or product terms that contain fewer variables. For example, the following 3-variable function:

a b c f(a,b,c)
0000
0010
0100
0111
1000
1010
1100
1111

has the canonical minterm representation: f = a'bc + abc, but it has an equivalent simplified form: f = bc. In this trivial example, it is obvious that bc = a'bc + abc, but the simplified form has both fewer product terms, and the term has fewer variables. The most simplified SoP representation of a function is referred to as a minimal SoP form.

In a similar manner, a canonical maxterm form can have a simplified PoS form.

While this example was easily simplified by applying normal algebraic methods [f = (a' + a) b c], in less obvious cases a convenient method for finding the minimal PoS/SoP form of a function with up to four variables is using a Karnaugh map.

The minimal PoS and SoP forms are very important for finding optimal implementations of boolean functions and minimizing logic circuits.

Application example

The sample truth tables for minterms and maxterms above are sufficient to establish the canonical form for a single bit position in the addition of binary numbers, but are not sufficient to design the digital logic unless your inventory of gates includes AND and OR. Where performance is an issue (as in the Apollo Guidance Computer), the available parts are more likely to be NAND and NOR because of the complementing action inherent in transistor logic. The values are defined as voltage states, one near ground and one near the DC supply voltage Vcc, e.g. +5 VDC. If the higher voltage is defined as the 1 "true" value, a NOR gate is the simplest possible useful logical element.

Specifically, a 3-input NOR gate may consist of 3 bipolar junction transistors with their emitters all grounded, their collectors tied together and linked to Vcc through a load impedance. Each base is connected to an input signal, and the common collector point presents the output signal. Any input that is a 1 (high voltage) to its base shorts its transistor's emitter to its collector, causing current to flow through the load impedance, which brings the collector voltage (the output) very near to ground. That result is independent of the other inputs. Only when all 3 input signals are 0 (low voltage) do the emitter-collector impedances of all 3 transistors remain very high. Then very little current flows, and the voltage-divider effect with the load impedance imposes on the collector point a high voltage very near to Vcc.

The complementing property of these gate circuits may seem like a drawback when trying to implement a function in canonical form, but there is a compensating bonus: such a gate with only one input implements the complementing function, which is required frequently in digital logic.

This example assumes the Apollo parts inventory: 3-input NOR gates only, but the discussion is simplified by supposing that 4-input NOR gates are also available (in Apollo, those were compounded out of pairs of 3-input NORs).

Canonical and non-canonical consequences of NOR gates

Fact #1: a set of 8 NOR gates, if their inputs are all combinations of the direct and complement forms of the 3 input variables ci, x, and y, always produce minterms, never maxterms—that is, of the 8 gates required to process all combinations of 3 input variables, only one has the output value 1. That's because a NOR gate, despite its name, could better be viewed (using De Morgan's law) as the AND of the complements of its input signals.

Fact #2: the reason Fact #1 is not a problem is the duality of minterms and maxterms, i.e. each maxterm is the complement of the like-indexed minterm, and vice versa.

In the minterm example above, we wrote u(ci, x, y) = m_1 + m_2 + m_4 + m_7 but to perform this with a 4-input NOR gate we need to restate it as a product of sums (PoS), where the sums are the opposite maxterms. That is,

u(ci, x, y) = AND(M_0,M_3,M_5,M_6) = NOR(m_0,m_3,m_5,m_6). Truth tables:

ci x y M0 M3 M5 M6 AND u(ci,x,y)
000011100
001111111
010111111
011101100
100111111
101110100
110111000
111111111

 

ci x y m0 m3 m5 m6 NOR u(ci,x,y)
000100000
001000011
010000011
011010000
100000011
101001000
110000100
111000011

In the maxterm example above, we wrote co(ci, x, y) = M_0 M_1 M_2 M_4 but to perform this with a 4-input NOR gate we need to notice the equality to the NOR of the same minterms. That is,

co(ci, x, y) = AND(M_0,M_1,M_2,M_4) = NOR(m_0,m_1,m_2,m_4). Truth tables:

ci x y M0 M1 M2 M4 AND co(ci,x,y)
000011100
001101100
010110100
011111111
100111000
101111111
110111111
111111111

 

ci x y m0 m1 m2 m4 NOR co(ci,x,y)
000100000
001010000
010001000
011000011
100000100
101000011
110000011
111000011

Design trade-offs considered in addition to canonical forms

One might suppose that the work of designing an adder stage is now complete, but we haven't addressed the fact that all 3 of the input variables have to appear in both their direct and complement forms. There's no difficulty about the addends x and y in this respect, because they are static throughout the addition and thus are normally held in latch circuits that routinely have both direct and complement outputs. (The simplest latch circuit made of NOR gates is a pair of gates cross-coupled to make a flip-flop: the output of each is wired as one of the inputs to the other.) There is also no need to create the complement form of the sum u. However, the carry out of one bit position must be passed as the carry into the next bit position in both direct and complement forms. The most straightforward way to do this is to pass co through a 1-input NOR gate and label the output co', but that would add a gate delay in the worst possible place, slowing down the rippling of carries from right to left. An additional 4-input NOR gate building the canonical form of co' (out of the opposite minterms as co) solves this problem.

co'(ci, x, y) = \mathrm{AND}(M_3,M_5,M_6,M_7) = \mathrm{NOR}(m_3,m_5,m_6,m_7).

Truth tables:

ci x y M3 M5 M6 M7 AND co'(ci,x,y)
000111111
001111111
010111111
011011100
100111111
101101100
110110100
111111000

 

ci x y m3 m5 m6 m7 NOR co'(ci,x,y)
000000011
001000011
010000011
011100000
100000011
101010000
110001000
111000100

The trade-off to maintain full speed in this way includes an unexpected cost (in addition to having to use a bigger gate). If we'd just used that 1-input gate to complement co, there would have been no use for the minterm m_7, and the gate that generated it could have been eliminated. Nevertheless, it's still a good trade.

Now we could have implemented those functions exactly according to their SoP and PoS canonical forms, by turning NOR gates into the functions specified. A NOR gate is made into an OR gate by passing its output through a 1-input NOR gate; and it is made into an AND gate by passing each of its inputs through a 1-input NOR gate. However, this approach not only increases the number of gates used, but also doubles the number of gate delays processing the signals, cutting the processing speed in half. Consequently, whenever performance is vital, going beyond canonical forms and doing the Boolean algebra to make the unenhanced NOR gates do the job is well worthwhile.

Top-down vs. bottom-up design

We have now seen how the minterm/maxterm tools can be used to design an adder stage in canonical form with the addition of some Boolean algebra, costing just 2 gate delays for each of the outputs. That's the "top-down" way to design the digital circuit for this function, but is it the best way? The discussion has focused on identifying "fastest" as "best," and the augmented canonical form meets that criterion flawlessly, but sometimes other factors predominate. The designer may have a primary goal of minimizing the number of gates, and/or of minimizing the fanouts of signals to other gates since big fanouts reduce resilience to a degraded power supply or other environmental factors. In such a case, a designer may develop the canonical-form design as a baseline, then try a bottom-up development, and finally compare the results.

The bottom-up development involves noticing that u = ci XOR (x XOR y), where XOR means eXclusive OR [true when either input is true but not when both are true], and that co = ci x + x y + y ci. One such development takes twelve NOR gates in all: six 2-input gates and two 1-input gates to produce u in 5 gate delays, plus three 2-input gates and one 3-input gate to produce co' in 2 gate delays. The canonical baseline took eight 3-input NOR gates plus three 4-input NOR gates to produce u, co and co' in 2 gate delays. If the circuit inventory actually includes 4-input NOR gates, the top-down canonical design looks like a winner in both gate count and speed. But if (contrary to our convenient supposition) the circuits are actually 3-input NOR gates, of which two are required for each 4-input NOR function, then the canonical design takes 14 gates compared to 12 for the bottom-up approach, but still produces the sum digit u considerably faster. The fanout comparison is tabulated as:

Variables Top-down Bottom-up
x 41
x' 43
y 41
y' 43
ci 41
ci' 43
M or m 4@1,4@2N/A
x XOR y N/A2
Misc N/A5@1
Max 43

What's a decision-maker to do? An observant one will have noticed that the description of the bottom-up development mentions co' as an output but not co. Does that design simply never need the direct form of the carry out? Well, yes and no. At each stage, the calculation of co' depends only on ci', x' and y', which means that the carry propagation ripples along the bit positions just as fast as in the canonical design without ever developing co. The calculation of u, which does require ci to be made from ci' by a 1-input NOR, is slower but for any word length the design only pays that penalty once (when the leftmost sum digit is developed). That's because those calculations overlap, each in what amounts to its own little pipeline without affecting when the next bit position's sum bit can be calculated. And, to be sure, the co' out of the leftmost bit position will probably have to be complemented as part of the logic determining whether the addition overflowed. But using 3-input NOR gates, the bottom-up design is very nearly as fast for doing parallel addition on a non-trivial word length, cuts down on the gate count, and uses lower fanouts ... so it wins if gate count and/or fanout are paramount!

We'll leave the exact circuitry of the bottom-up design of which all these statements are true as an exercise for the interested reader, assisted by one more algebraic formula: u = ci(x XOR y) + ci'(x XOR y)']'. Decoupling the carry propagation from the sum formation in this way is what elevates the performance of a carry-lookahead adder over that of a ripple carry adder.

To see how NOR gate logic was used in the Apollo Guidance Computer's ALU, visit http://klabs.org/history/ech/agc_schematics/index.htm, select any of the 4-BIT MODULE entries in the Index to Drawings, and expand images as desired.

See also

Footnotes

  1. ↑ Eldon C. Hall, Journey to the Moon: The History of the Apollo Guidance Computer, AIAA 1996. ISBN 1-56347-185-X

References

External links

The Wikibook How to search has a page on the topic of: Boolean Logic
The Wikibook Electronics has a page on the topic of: Boolean Algebra
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