Load/store architecture

In computer engineering a load/store architecture only allows memory to be accessed by load and store operations, and all values for an operation need to be loaded from memory and be present in registers. Following the operation, the result needs to be stored back to memory.[1]

For instance, in a load/store approach both operands for an ADD operation must be in registers. This differs from a register memory architecture in which one of the operands for the ADD operation may be in memory, while the other is in a register.[1]

The earliest example of a load/store architecture was the CDC 6600.[2] Almost all vector processors use the load/store approach.[3]

RISC systems such as PowerPC, SPARC, RISC-V, ARM or MIPS use the load/store architecture.[1]

See also

References

  1. 1 2 3 Computer architecture: pipelined and parallel processor design by Michael J. Flynn 1995 ISBN 0867202041 pages 9-12
  2. ↑ Computer architecture: pipelined and parallel processor design by Michael J. Flynn 1995 ISBN 0867202041 pages 54-56
  3. ↑ Memory systems and pipelined processors by Harvey G. Cragon 1996 ISBN 0867204745 pages 512-513
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