Cannonlake
CannonlakeCreated |
H2 2017[1] |
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Transistors |
10 nm transistors |
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Architecture |
x86 |
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Instructions |
MMX, AES-NI, CLMUL, FMA3 |
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Extensions |
- x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, AVX-512, TXT, TSX
- VT-x, VT-d
|
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Socket |
LGA 1151 |
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Predecessor |
Kaby Lake (semi-Tock)[2] |
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Successor |
- Ice Lake (Tock)[2]
- Tiger Lake (semi-Tock)[2]
|
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Brand name(s) |
- Core M
- Core i3
- Core i5
- Core i7
- Celeron
- Pentium
- Xeon
|
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Cannonlake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Skylake microarchitecture, expected to be released in the second half of 2017.[1][3] As a die shrink, Cannonlake is a "tick" in Intel's "tick-tock" execution plan as the next step in semiconductor fabrication.[4] Cannonlake will be used in conjunction with Intel 200 Series chipsets, also known as Union Point. The platform as a whole will be named Union Bay.[4]
It has been speculated for a long time that reaching smaller process nodes would become impractical, leading to the end of Moore's Law. Intel however believes that it will be possible to reach at least 7 nm, though it will perhaps require use of materials other than silicon,[5] such as indium gallium arsenide (InGaAs).
The successors of the Cannonlake microarchitecture will be Icelake and Tigerlake, which will represent two consecutive "tocks" of the Intel Tick-Tock Model.[6][7]
Features
See also
References