Glitch removal

a and b are input to OR gate with output x. x and c are input to AND gate with output y

Glitch removal is the elimination of glitches—unnecessary signal transitions without functionality—from electronic circuits. Power dissipation of a gate occurs in two ways: Static power dissipation and Dynamic power dissipation. Glitch power comes under dynamic dissipation in the circuit and is directly proportional to switching activity. Glitch power dissipation is 20%-70% of total power dissipation and hence glitching should be eliminated for low power design.

Switching activity occurs due to Signal transitions which are of two types: functional transition and a glitch. Switching power dissipation is directly proportional to the switching activity (α), load capacitance (C), Supply voltage (V), and clock frequency (f) as:

Switching activity means transition to different levels. Glitches are dependent on signal transitions and more glitches results in higher power dissipation. As per above equation switching power dissipation can be controlled by controlling switching activity (α), voltage scaling etc.

Glitch reduction techniques

Reducing switching activity

As discussed, more transition results in more glitches and hence more power dissipation. To minimize glitch occurrence, switching activity should be minimized. For example, in the design of 4 bit counter if gray code is used instead of binary code then switching activity is reduced by a great extent. As counting from 0000 to 0101, a usual binary counter takes 5 transitions whereas gray code implemented counter takes only 2 transitions and hence switching activity is reduced.

Transition in Binary counter
Transition in gray code counter

Gate freezing

Gate freezing minimizes power dissipation by eliminating glitching. It relies on the availability of modified standard library cells such as the so-called F-Gate. This method consists of transforming high glitch gates into modified devices which filter out the glitches when a control signal is applied. When the control signal is high, the F-Gate operates as normal but when the control signal is low, the gate output is disconnected from the ground. As a result it can never be discharged to logic 0 and glitches are prevented.

Hazard filtering and balanced path delay

Balanced path delay technique

Hazards in digital circuits are unnecessary transitions due to varying path delays in the circuit. Balanced path delay techniques can be used for resolving differing path delays. To make path delays equal, buffer insertion is done on the faster paths. Balanced path delay will avoid glitches in the output.

Hazard filtering is another way to remove glitching. In hazard filtering gate propagation delays are adjusted. This results in balancing all path delays at the output.

Hazard filtering is preferred over path balancing as path balancing consumes more power due to the insertion of additional buffers.

Gate sizing

Gate upsizing and gate downsizing techniques are used for path balancing. A gate is replaced by a logically equivalent but differently-sized cell so that delay of the gate is changed. Because increasing the gate size also increases power dissipation, gate-upsizing is only used when power saved by glitch removal is more than the power dissipation due to the increase in size. Gate sizing affects glitching transitions but does not affect the functional transition.

Multiple threshold transistor

The delay of a gate is a function of its threshold voltage. Non critical paths are selected and threshold voltage of the gates in these paths is increased. This results in balanced propagation delay along different paths converging at the receiving gate. Performance is maintained since it is determined by the time required by the critical path. A higher threshold voltage also reduces the leakage current of a path.

See also

References

  1. Hyungoo Lee, Hakgun Shin, Juho Kim, "Glitch Elimination by Gate Freezing, Gate Sizing and Buffer Insertion for Low Power Optimization Circuit" IEEE Transactions 2126-2131. doi: 10.1109/IECON.2004.1432125
  2. Olivier Coudert, Gate Sizing for Constrained Delay/Power/Area Optimization, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. XX, NO. Y, SEPTEMBER 1997. DOI: 10.1109/92.645073
  3. Sachin S. Sapatnekar, Weitong Chuang, Power-Delay Optimizations in Gate Sizing. http://www.ece.umn.edu/~sachin/jnl/todaes00wc.pdf
  4. Warren Shum and Jason H. Anderson, “FPGA Glitch Power Analysis and Reduction”, International Symposium on Low power electronics and design (ISLPED) 2011, page no. 27-32.
  5. Zhanping Chen, Liqiong Wei, Kaushik Roy, REDUCING GLITCHING AND LEAKAGE POWER IN LOW VOLTAGE CMOS CIRCUITS, March 1997, Purdue University School of Electrical and Computer Engineering. http://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1084&context=ecetr

External links

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