Esterel Studio
Esterel Studio is a design environment based on the Esterel language. It is optimized for hardware IPs (such as DMAs, protocols, cache controllers, I/O subsystems, etc.) dedicated at capturing formal design specifications, enabling formal verification of properties early in the design phase, and automating the production of synthesizable RTL (VHDL and Verilog), both for prototyping and production purposes.
Features
- Formal executable specifications.
- Verification of properties and assertions.
- synchronous dataflow design.
- Generate specification in VHDL or Verilog formats.
- Generate C, C++, or SystemC code.
- ECO support.
See also
External links
This article is issued from Wikipedia - version of the Monday, November 04, 2013. The text is available under the Creative Commons Attribution/Share Alike but additional terms may apply for the media files.