Digital clock manager

A digital clock manager (DCM) is a feature available on some FPGAs (notably ones produced by Xilinx), for manipulating clock signals by: ^[1]

• Multipling or dividing an incoming clock (DFS).
• Reconditioning a clock for a steady duty cycle.
• Adding a phase shift using a Delay-locked loop
• Eliminating clock skew within an FPGA design.

See also

• Clock signal
• Delay-locked loop
• Phase-locked loop
• Field-programmable gate array

References

1. ↑ "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs" (PDF).  070804 xilinx.com