ARM Cortex-A72
The ARM Cortex-A72 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A72 is an out-of-order superscalar pipeline.[1] It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
The base-line architecture for the Cortex-A72 was the Cortex-A57; however, the design is more than just a simple revision. [2] The designers of the Cortex-A72 had three major themes when designing the new core: pushing the performance to the next generation; reducing the power significantly so that it can sustain maximum frequency performance; and reducing the area used by the design, again contributing to a reduction in power, but also enabling low cost designs as well. [3]
Overview
- Pipelined processor with deeply out of order, speculative issue 3-way superscalar execution pipeline
- DSP and NEON SIMD extensions are mandatory per core
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- Thumb-2 instruction set encoding reduces the size of 32-bit programs with little impact on performance.
- TrustZone security extensions
- Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
- 32 KiB data (2-way set-associative) + 48 KiB instruction (3-way set-associative) L1 cache per core
- Integrated low-latency level-2 (16-way set-associative) cache controller, 512 KB to 4 MB configurable size per cluster
- 48-entry fully associative L1 instruction Translation Lookaside Buffer (TLB) with native support for 4 KiB, 64 KiB, and 1 MB page sizes
- 4-way set-associative of 1024-entry L2 TLB
- Sophisticated branch prediction algorithm that significantly increases performance and reduces energy from mispredictionand speculation
- Early IC tag –3-way L1 cache at direct-mapped power*
- Regionalized TLB and μBTB tagging
- Small-offset branch-target optimizations
- Suppression of superfluous branch predictor accesses
See also
References
External links
Application ARM-based chips |
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- Actions ATM702x, ATM703x
- Altera Cyclone V, Arria V/10
- Amlogic AML8726, MX, M6x, M801, M802/S802, S812, T866
- Apple A5, A5X
- Broadcom VideoCore BCM21xxx, BCM28xxx
- Freescale i.MX6x
- HiSilicon K3V2
- InfoTM iMAPx912
- Leadcore LC1810, LC1811
- MediaTek MT65xx
- Nvidia Tegra, 2, 3, 4i
- Nufront NuSmart 2816M, NS115, NS115M
- Renesas EMMA EV2, R-Car H1, RZ/A
- Rockchip RK292x, RK30xx, RK31xx
- Samsung Exynos 4
- ST-Ericsson NovaThor
- Telechips TCC8803
- Texas Instruments OMAP 4
- VIA WonderMedia WM88x0, 89x0
- Xilinx Zynq-7000
- ZiiLABS ZMS-20, ZMS-40
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| Application Processors (64-bit) | |
- Actions S900
- Allwinner A64, H64
- Altera Stratix 10
- Amlogic S905
- EZchip TILE-Mx100
- Marvell Armada PXA1928, Mobile PXA1908/PXA1936
- MediaTek MT673x, MT675x, MT6795, MT8732, MT8752, Helio X10
- Qualcomm Snapdragon 410
- Rockchip RK3368
- Xilinx ZynqMP
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