ARM Cortex-A53
The ARM Cortex-A53 is a microarchitecture implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A53 is an superscalar processor capable of dual-issuing some instructions.[1] It is available as SIP core to licensees, and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration.
Overview
- 8-stage pipelined processor with 2-way superscalar execution pipeline
- DSP and NEON SIMD extensions are mandatory per core
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- TrustZone security extensions
- 64-Byte cache lines
- 10-entry L1 TLB, and 512-entry L2 TLB
- 4 Kb conditional branch predictor, 256-entry indirect branch predictor
See also
References
External links
Application ARM-based chips |
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- Actions ATM702x, ATM703x
- Altera Cyclone V, Arria V/10
- Amlogic AML8726, MX, M6x, M801, M802/S802, S812, T866
- Apple A5, A5X
- Broadcom VideoCore BCM21xxx, BCM28xxx
- Freescale i.MX6x
- HiSilicon K3V2
- InfoTM iMAPx912
- Leadcore LC1810, LC1811
- MediaTek MT65xx
- Nvidia Tegra, 2, 3, 4i
- Nufront NuSmart 2816M, NS115, NS115M
- Renesas EMMA EV2, R-Car H1, RZ/A
- Rockchip RK292x, RK30xx, RK31xx
- Samsung Exynos 4
- ST-Ericsson NovaThor
- Telechips TCC8803
- Texas Instruments OMAP 4
- VIA WonderMedia WM88x0, 89x0
- Xilinx Zynq-7000
- ZiiLABS ZMS-20, ZMS-40
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| ARMv7-A compatible | |
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| Application Processors (64-bit) | |
- Actions S900
- Allwinner A64, H64
- Altera Stratix 10
- Amlogic S905
- EZchip TILE-Mx100
- Marvell Armada PXA1928, Mobile PXA1908/PXA1936
- MediaTek MT673x, MT675x, MT6795, MT8732, MT8752, Helio X10
- Qualcomm Snapdragon 410
- Rockchip RK3368
- Xilinx ZynqMP
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