SpiNNaker

SpiNNaker: Spiking Neural Network Architecture
Mission statement novel computer architecture inspired by the working of the human brain
Founder Steve Furber
Website spinnaker.cs.manchester.ac.uk

SpiNNaker (Spiking Neural Network Architecture) is a computer architecture designed by the Advanced Processor Technologies Research Group (APT) at the School of Computer Science, University of Manchester, led by Steve Furber, to simulate the human brain. It uses ARM processors in a massively parallel computing platform,[1][1] based on a six-layer thalamocortical model developed by Eugene Izhikevich.[2][3][4][5][6][7][8][9]

SpiNNaker is being used as the Neuromorphic Computing Platform for the Human Brain Project.[10][11]

References

  1. ↑ 1.0 1.1 SpiNNaker Home Page, University of Manchester, retrieved 11 June 2012
  2. ↑ Furber, S. B.; Galluppi, F.; Temple, S.; Plana, L. A. (2014). "The SpiNNaker Project". Proceedings of the IEEE: 1. doi:10.1109/JPROC.2014.2304638.
  3. ↑ Xin Jin; Furber, S. B.; Woods, J. V. (2008). "Efficient modelling of spiking neural networks on a scalable chip multiprocessor". 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence). pp. 2812–2819. doi:10.1109/IJCNN.2008.4634194. ISBN 978-1-4244-1820-6.
  4. ↑ A million ARM cores to host brain simulator News article on the project in the EE Times
  5. ↑ Temple, S.; Furber, S. (2007). "Neural systems engineering". Journal of the Royal Society Interface 4 (13): 193. doi:10.1098/rsif.2006.0177. A manifesto for the SpiNNaker project, surveying and reviewing the general level of understanding of brain function and approaches to building computer modelof the brain.
  6. ↑ Plana, L. A.; Furber, S. B.; Temple, S.; Khan, M.; Shi, Y.; Wu, J.; Yang, S. (2007). "A GALS Infrastructure for a Massively Parallel Multiprocessor". IEEE Design & Test of Computers 24 (5): 454. doi:10.1109/MDT.2007.149. A description of the Globally Asynchronous, Locally Synchronous (GALS) nature of SpiNNaker, with an overview of the asynchronous communications hardware designed to transmit neural 'spikes' between processors.
  7. ↑ Navaridas, J.; Luján, M.; Miguel-Alonso, J.; Plana, L. A.; Furber, S. (2009). "Understanding the interconnection network of SpiNNaker". Proceedings of the 23rd international conference on Conference on Supercomputing - ICS '09. p. 286. doi:10.1145/1542275.1542317. ISBN 9781605584980. Modelling and analysis of the SpiNNaker interconnect in a million-core machine, showing the suitability of the packet-switched network for large-scale spiking neural network simulation.
  8. ↑ Rast, A.; Galluppi, F.; Davies, S.; Plana, L.; Patterson, C.; Sharp, T.; Lester, D.; Furber, S. (2011). "Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware". Neural Networks 24 (9): 961–978. doi:10.1016/j.neunet.2011.06.014. PMID 21778034. A demonstration of SpiNNaker's ability to simulate different neural models (simultaneously, if necessary) in contrast to other neuromorphic hardware.
  9. ↑ Sharp, T.; Galluppi, F.; Rast, A.; Furber, S. (2012). "Power-efficient simulation of detailed cortical microcircuits on SpiNNaker". Journal of Neuroscience Methods 210 (1): 110–118. doi:10.1016/j.jneumeth.2012.03.001. PMID 22465805. Four-chip, real-time simulation of a four-million-synapse cortical circuit, showing the extreme energy efficiency of the SpiNNaker architecture
  10. ↑ Calimera, A; Macii, E; Poncino, M (2013). "The Human Brain Project and neuromorphic computing". Functional neurology 28 (3): 191–6. PMC 3812737. PMID 24139655.
  11. ↑ Monroe, D. (2014). "Neuromorphic computing gets ready for the (really) big time". Communications of the ACM 57 (6): 13–15. doi:10.1145/2601069.