Silvaco

Silvaco, Inc.

Type	Private Company
Industry	Software & Programming
Founded	1984
Founder	Ivan Pesic
Headquarters	Santa Clara, California
Key people	Iliya Pesic, Chairman David Halliday, CEO[1]
Website	www.silvaco.com

Simucad Design Automation, Inc.

Type	Private Company
Industry	Software & Programming
Founded	1981, 2004
Headquarters	Santa Clara, California

Silvaco, inc. is a privately owned provider of electronic design automation (EDA) software^[2] and TCAD process and device simulation software.^[3] Silvaco was founded in 1984 and is headquartered in Santa Clara, California, and in 2006 the company had about 250 employees worldwide.

Silvaco provides analog semiconductor process, device and design automation solutions in CMOS, bipolar, SiGe and compound technologies. Customers include leading fabless semiconductor companies, integrated semiconductor manufacturers, foundries, and universities worldwide.

History

Founded by Dr Ivan Pesic (September 13, 1951, Resnik, Montenegro — October 20, 2012, Japan^[1][4]) in 1984, the company is privately held and internally funded. It is headquartered in Santa Clara, California, with eight offices worldwide including US offices in Austin, Texas, North Chelmsford, Massachusetts, and Phoenix, Arizona.

In 2012 David Halliday^[1] was appointed CEO after Ivan Pesic the company founder passed away from cancer. David Halliday joined Silvaco in 1992 and prior to his appointment as CEO he was the company COO. David also held the office of Vice President of Engineering for much of his tenure at Silvaco.

In 2003 Silvaco acquired EDA Pioneer Simucad, for its brand name as well as for its SILOS and Hyperfault simulators. Simucad was one of the oldest companies in the IC design industry.^[5][6] The original Simucad was formed in 1981 with pioneering business in Verilog simulation. It was acquired by HHB Systems, which in its turn was acquired by Daisy Systems in 1980s and in the early 1990s Simucad was spun off as a management buyout. After purchasing Simucad in 2003 Silvaco re-launched the brand by spinning out its EDA product line in 2006 under the Simucad name.^[5][7] Simucad acquired ownership all of Silvaco's simulation and CAD products and intellectual property, most notably the SmartSpice circuit simulator.^[8] As of March 1, 2010, Simucad Design Automation and Silvaco Data Systems were merged back together forming Silvaco, Inc.

Products

Silvaco delivers EDA and Stanford-based TCAD products with support and engineering services to provide semiconductor process and device simulation solutions. Worldwide customers include leading foundries, fabless semiconductor companies, integrated semiconductor manufacturers, universities, and semiconductor designers.

TCAD products

• Process Simulation
  • Victory Process is a 3D Process Simulator. It includes a process flow core simulator and three advanced simulation modules: Monte Carlo Implant, Advanced Diffusion and Oxidation, and Physical Etch and Deposit.
  • Victory Cell is a 3D Process Simulator for Large Structures. It is suitable for CMOS image sensors, TFT arrays, power devices, and other large geometry structures.
  • Athena is a group of process simulation products that enables process and integration engineers to develop and optimize semiconductor manufacturing processes. ATHENA provides a platform for simulating ion implantation, diffusion, etching, deposition, lithography, oxidation, and silicidation of semiconductor materials. It replaces costly wafer experiments with simulations.^[9]
  • Athena 1D 1D Process Simulator is a 1D mode of operation of the industry standard Athena 2D Process Simulator.
• Device Simulation
  • Victory Device is a general-purpose 3D device simulator using a tetrahedral meshing engine for fast and accurate simulation of complex 3D geometries.
  • Atlas is a group of device simulation products enables device technology engineers to simulate the electrical, optical, and thermal behavior of semiconductor devices. It provides a physics-based, modular, and extensible platform to analyze DC, AC, and time domain responses for all semiconductor based technologies in 2 and 3 dimensions.
• Stress Simulation
  • Victory Stress is a generic 3D stress simulator designed to calculate stresses and mobility enhancement factors for any 3D structure using comprehensive material stress models.
• Other tools
  • Interactive Tools, a suite of pre and post processing tools that provide interactive GUI-based pre and post processing services to Silvaco’s 1D, 2D and 3D TCAD simulators.
  • Virtual Wafer Fab or "VWF" is a group of TCAD products that automate and emulate physical wafer manufacturing. These tools facilitate the input, execution, run-time optimization, and results processing of TCAD simulations into a flow managed through a common database. It can be used for such tasks as designing more efficient solar cells for use in space.^[10]

EDA products

The company supplies integrated EDA software in the areas of Analog/Mixed-Signal/RF, Custom IC CAD, Interconnect Modeling, and Digital CAD.

• Analog/Mixed-Signal/RF products
  • Utmost III SPICE modeling software generates SPICE models for analog, digital, mixed-signal, and RF applications.
  • Utmost IV optimization module provides a database-driven environment for the generation of SPICE models and macro-models for analog, mixed-signal and RF applications.
  • Spayn, meaning Statistical Parameter and Yield Analysis, is a statistical modeling tool for analyzing variances from model parameter extraction sequences, electrical test routines, and circuit test measurements.
  • Gateway is a schematic editor. It is a front end for Silvaco's Analog/Mixed Signal/RF IC Design Platform, and is integrated with the company's circuit simulation, layout, DRC/LVS/LPE, and parasitic extraction tools.
  • SmartSpice is an analog circuit simulator used in the design of analog circuits and analog mixed-signal circuits. It can analyze critical nets and characterize cell libraries.
  • SmartSpice RF is a harmonic balance based RF simulator. It provides a set of steady-state large-signal analyses and measurements to design GHz range RF ICs driven with multi-tone sources.
  • Harmony is an analog and mixed-signal circuit simulator. It simulates circuitry expressed in Verilog, SPICE, Verilog-A and Verilog-AMS, and dynamically links in the capabilities of the SmartSpice Circuit Simulator and SILOS Verilog Simulator at run time.
  • Verilog-A is a language for SmartSpice. Compiled or interpreted Verilog-A language combined with SmartSpice provides designers with an environment for the design and verification of analog and mixed-signal circuits.
• Custom IC CAD
  • Expert is a layout editor. It offers layout viewing, editing features, and scripting for automation with parameterized cells (PCells).
  • Guardian is a suite of DRC/LVS/LPE physical verification products. They provide verification of analog, mixed signal and RF IC designs, perform design rule checks (DRC), layout vs. schematic (LVS) comparisons, and layout parameter extractions (LPE).
  • Hipex is a set of full-chip parasitic extraction products. They perform extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists using nanometer process technology.
• Interconnect Modeling
  • Quest is a high frequency parasitic extractor. It calculates 3D frequency-dependent inductance, resistance, capacitance and capacitive loss for any multi-port network for RF SPICE analysis.
  • Clever is a physics-based parasitic extractor. It uses 3D field solvers to convert the mask data of a cell and relevant process information into a SPICE netlist. This process removes inaccuracies resulting from traditional, rule-based parasitic extractors.
  • Stellar is a core parasitic extractor. It fills the circuit size gap between typical small cell solvers and full chip extractors.
  • Exact is a full chip LPE rule file generator
• Digital CAD
  • Silos is an IEEE-1364-2001 compliant Verilog simulator. It offers debugging features in a design environment for FPGA, PLD, ASIC, and custom digital designs.
  • HyperFault is an IEEE-1364-2001 compliant mixed-level fault simulator that analyses test vectors’ ability to detect faults.
  • AccuCell is a characterization and modeling tool that characterizes and validates standard cell libraries, I/Os, and custom cells.
  • AccuCore provides transistor and gate level full-chip STA with automatic block characterization.
  • Catalyst AD is a SPICE Netlist to Verilog Gates Converter
  • Catalyst DA is a Verilog Netlist to SPICE Netlist Converter
  • Spider provides a place and Route Design Flow

Process Design Kits (PDKs)

Silvaco offers process design kits (PDKs) for analog, mixed-signal and RF design teams. These are collections of verified data files that are used by a set of custom IC design EDA tools to provide a design flow. Such data files include schematic symbols, parameterized cells (PCells), DRC/LVS runsets, parasitic extraction runsets, and scripts to automate the generation and verification of design data.

Foundry process-specific models, symbols, and rule decks are integrated and tested with Silvaco custom IC design tools and PCells to create an AMS/RF design environment.

Litigation

Silvaco has been involved in litigation against such companies as Circuit Semantics, Inc. (CSI),^[11] Technology Modeling Associates, MetaSoftware and Avanti Corporation for theft of trade secrets. Silvaco won a $20 million judgment from Avanti just prior to the latter company's acquisition by Synopsys.^[12] In 2008, legal action by Silvaco against Cypress Semiconductor, Inc. led the California Court of Appeal to make a ruling clarifying when the statute of limitations for theft of trade secrets begins. The ruling stated that "statute of limitations on a cause of action for misappropriation begins to run when the plaintiff has any reason to suspect that the third party knows or reasonably should know that the information is a trade secret."^[13][14][15]

In Silvaco Data Systems v. Intel Corp., Silvaco sued Intel for misappropriation of trade secrets (deriving from the CSI case), but ultimately lost in both the trial and appellate courts.

References