Sarita Adve
| Sarita V. Adve | |
|---|---|
| Institutions |
University of Illinois at Urbana-Champaign Rice University |
| Alma mater |
Indian Institute of Technology Bombay (B.Tech) University of Wisconsin - Madison (M.S., PhD) |
Sarita Adve is Professor in the Department of Computer Science and a PI for the Universal Parallel Computing Research Center at the University of Illinois at Urbana-Champaign. Her research interests are in computer architecture and systems, parallel computing, and power and reliability-aware systems.
Dr. Adve's most significant research contributions are in the areas of memory consistency models for multiprocessors (she co-developed the memory models for the C++ and Java programming languages, which are based on her early work on data-race-free models); hardware reliability (she co-developed the concept of lifetime reliability aware architectures and dynamic reliability management); power management (she led the design of one of the first systems to implement cross-layer energy management); exploiting instruction-level parallelism (ILP) for memory system performance (she co-authored some of the first papers on exploiting ILP for memory level parallelism); and evaluation techniques for shared-memory multiprocessors with ILP processors (she led the development of the widely used RSIM architecture simulator).
Dr. Adve received her Ph.D. and M.S. degrees in Computer Science from the University of Wisconsin–Madison in 1993 and 1989 respectively, and the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology-Bombay in 1987. Before joining Illinois, she was on the faculty at Rice University from 1993 to 1999. Dr. Adve received the ACM SIGARCH Maurice Wilkes award in 2008, an IBM faculty award in 2005, was named a UIUC University Scholar in 2004, received an Alfred P. Sloan Research Fellowship in 1998, an IBM University Partnership award in 1997 and 1998, and a National Science Foundation CAREER award in 1995. She served on the NSF CISE directorate's advisory committee from 2003 to 2005 and on the expert group to revise the Java memory model from 2001 to 2005. She currently serves on the ACM SIGARCH board of directors. She was named a Fellow of the ACM in 2010.[1]
Current research affiliations
- Universal Parallel Computing Research Center (UPCRC) at Illinois
- Power and Reliability Aware Systems
- SWAT: SoftWare Anomaly Treatment
- RAMP: Reliability-Aware MicroProcessors
- ALP: All Levels of Parallelism for emerging multimedia workloads
- Global Resource Adaptation through CoopEration for energy in mobile multimedia systems
- Energy and Thermal Management in Data Centers
See also
- Sarita Adve's Homepage
- Parallel Computing Research at Illinois: The UPCRC Agenda
- Parallel@Illinois
- Illinois Department of Computer Science
- Sarita Adve Honored for Work on Memory Consistency Models