Physical Coding Sublayer
The Physical Coding Sublayer (PCS) is a networking protocol sublayer in the Fast Ethernet, gigabit Ethernet, and 10 Gigabit Ethernet standards. It resides at the top of the physical layer (PHY), and provides an interface between the Physical Medium Attachment (PMA) sublayer and the Media Independent Interface (MII). It is responsible for data encoding/decoding, scrambling/descrambling, alignment marker insertion/removal, block and symbol redistribution, and lane block synchronization and deskew.[1]
Description
The Ethernet PCS sublayer is at the top of the Ethernet physical layer (PHY). The hierarchy is as follows:
- Data Link Layer (Layer 2)
- LLC (Logical Link Control Sublayer)
- MAC (Media Access Control Sublayer)
- RS (Reconciliation Sublayer) - This sublayer processes PHY Local/Remote Fault messages and handles DDR conversion
- PHY Layer (Layer 1)
- PCS (Physical Coding Sublayer) - This sublayer determines when a functional link has been established, provides rate difference compensation, and performs coding such as 64b/66b encoding and
scrambling/descrambling - PMA (Physical Medium Attachment Sublayer) - This sublayer performs PMA framing, octet synchronization/detection, and
scrambling/descrambling - PMD (Physical Medium Dependent Sublayer) - This sublayer consists of a transceiver for the physical medium
- PCS (Physical Coding Sublayer) - This sublayer determines when a functional link has been established, provides rate difference compensation, and performs coding such as 64b/66b encoding and
Physical Coding Sublayer (PCS) specifications
Gigabit Ethernet
- 1000BASE-X for fiber and 150 Ω balanced copper (twinaxial) uses 8b/10b encoding with a symbol rate of 1.25 GBd.[2]
- 1000BASE-T for twisted pair copper splits the data into four lanes and uses four-dimensional, five-level (quinary) Trellis modulation with PAM-5 and a symbol rate of 125 MBd.[3]
10 Gigabit Ethernet
- 10GBASE-R (LAN) is the serial encoded PCS using 64b/66b encoding that allows for Ethernet framing at a rate of 10.3125 Gbit/s. This rate does not match the rate 9.953 Gbit/s used in SONET and SDH and is not supported over a WAN based on SONET or SDH.
- 10GBASE-X (LAN) uses similar coding methods as 10GBASE-R but is only used in the definition of 10GBASE-LX4. This is mainly because LX4 operates on both single and multimode fibers, giving it a unique set of specifications as defined in its PMD.
- 10GBASE-W (WAN) defines WAN encoding for 10GbE, it encodes the frames so that they are compatible with SONET STS-192c data rates and SDH VC-4-64 transmission standards allowing for 10 Gbit/s transmission across a WAN. It does this by wrapping the 64/66b payload into a SONET frame, making the effective rate 9.95 Gbit/s.
40/100 Gigabit Ethernet
- 40GBASE-R and 100GBASE-R use 64b/66b encoding over multiple lanes of 10.3125 GBd or 25.78125 GBd each. These lanes – four for 40 Gbit/s, four or ten for 100 Gbit/s per direction – are either transmitted separately over short distance or together with coarse wavelength division multiplexing on long distance fiber (-LR).[4]
Lattice Semiconductor multi-protocol
"PCS logic can be configured to support numerous industry-standard, high-speed serial data transfer protocols."[5]
References
- ↑ Spurgeon, Charles (2014). Ethernet: The Definitive Guide. O'Reilly. p. 198.
- ↑ IEEE 802.3-2012 Clause 36
- ↑ IEEE 802.3-2012 Clause 40
- ↑ IEEE 802.3 Clauses 82-89
- ↑ "LatticeECP3 SERDES/PCS Usage Guide". Lattice semiconductor Corporation: p 8–1. Retrieved 2014-09-03.
- Barbieri, Alessandro. "10 GbE and Its X Factors". Packet: Cisco Systems Users Magazine 17 (3): 25–28. Retrieved 2007-12-31.