Nehalem (microarchitecture)

Nehalem

L1 cache	64 KB per core
L2 cache	256 KB per core
L3 cache	4 MB to 24 MB shared
Model	Celeron Series
Created	November 2008
Transistors	731M 45 nm (C0, D0)
Architecture	Nehalem x86
Instructions	MMX
Extensions	x86-64, Intel 64 SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 VT-x, VT-d
Socket(s)	LGA 1156 LGA 1366 LGA 1567 µPGA 988
Predecessor	Core (tock) Penryn (tick)
Successor	Westmere (tick) Sandy Bridge (tock)

Nehalem /nəˈheɪləm/^[1] is the codename for an Intel processor microarchitecture, which is the successor to the older Core microarchitecture.^[2] A preview system with two Nehalem processors was shown at Intel Developer Forum in 2007, and the first processor released with the Nehalem architecture was the desktop Core i7,^[3] which was released in November 2008.

"Nehalem" is a recycled Intel codename and namesake of the Nehalem River.^[4][5] It is an architecture that differs radically from Netburst, while retaining some of the latter's minor features. Nehalem-based microprocessors use the 45 nm process, run at higher clock speeds, and are more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores.

Nehalem was replaced with the Sandy Bridge microarchitecture, released in January 2011.

Technology

Microarchitecture of a processor core in the quad-core implementation

• Hyper-threading reintroduced.
• 4–12 MB L3 cache
• Second-level branch predictor and translation lookaside buffer
• Native (all processor cores on a single die) quad- and octa-core processors
• Intel QuickPath Interconnect in high-end models replacing the legacy front side bus
• 64 KB L1 cache per core (32 KB L1 data and 32 KB L1 instruction), and 256 KB L2 cache per core.
• Integration of PCI Express and DMI into the processor in mid-range models, replacing the northbridge
• Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2 channels
• Second-generation Intel Virtualization Technology, which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting ^[6]
• SSE4.2 and POPCNT instructions
• Macro-op fusion now works in 64-bit mode.
• 20 to 24 pipeline stages^[7]

Translation lookaside buffer sizes^[8]

Cache		Page Size
Name	Level	4 KB	2 MB
DTLB	1st	64	32
ITLB	1st	128	7 / logical core
STLB	2nd	512	none

Performance and power improvements

It has been reported that Nehalem has a focus on performance, thus the increased core size.^[9] Compared to Penryn, Nehalem has:

• 10–25% better single-threaded performance / 20–100% better multithreaded performance at the same power level
• 30% lower power consumption for the same performance
• On average, Nehalem provides a 15–20% clock-for-clock increase in performance per core.

Overclocking is possible with Bloomfield processors and the X58 chipset. Lynnfield processors use a PCH removing the need for a northbridge chipset.^[10]

Nehalem processors incorporate SSE 4.2 SIMD instructions, adding seven new instructions to the SSE 4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate overhead on atomic operations such as the LOCK CMPXCHG compare-and-swap instruction.^[11]

Variants

• Lynnfield processors feature integrated PCIe 1 x16 or 2 x8.
• ¹ 6500 series scalable up to 2 sockets, 7500 series scalable up to 4/8 sockets.^[12]

Server and desktop processors

• Intel states the Gainestown processors have six memory channels. Gainestown processors have dual QPI links and have a separate set of memory registers for each link in effect, a multiplexed six-channel system.^[25][26]

Mobile processors

Roadmap

The successor to Nehalem and Westmere is Sandy Bridge.

See also

• List of Intel CPU microarchitectures

References

Further reading

External links

• Nehalem processor at Intel.com