Makefile

Makefile
Original author(s) Stuart Feldman
Operating system Unix-like
Type Software development tools
Website GNU Makefile

Makefile(s) are text files written in a certain prescribed syntax. Together with Make Utility, it helps build a software from its source files, a way to organize code, and its compilation and linking.

Overview

Most often, the Makefile tells make how to compile and link a program. Using C/C++ as an example, when a C/C++ source file is changed, it must be recompiled. If a header file has changed, each C/C++ source file that includes the header file must be recompiled to be safe. Each compilation produces an object file corresponding to the source file. Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable program.[1] These instructions with their dependencies are specified in a Makefile. If none of the files that are prerequisites have been changed since the last time the program was compiled, no actions take place. For large software projects, using Makefiles can substantially reduce build times if only a few source files have changed.

Operating Systems

Unix-like

Makefiles originated in Unix like systems and is still the primary software build mechanism.

Microsoft Windows

Windows supports a variation of makefiles with its nmake utility. Standard Unix like makefiles can be executed in Windows in a Cygwin environment.

However, Visual Studio is a very popular software development environment in Windows which does not use makefiles. The equivalent of a Makefile is managed by Visual Studio Project and Solution files.[2]

Contents

Makefiles contain five kinds of things: explicit rules, implicit rules, variable definitions, directives, and comments.

Rules

A makefile consists of “rules” with the following construct.

target: dependencies
Tab  system command(s)

Note: It is important to insert a Tab character before the commands.

A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as 'clean'.

A dependency (also called prerequisite) is a file that is used as input to create the target. A target often depends on several files. However, the rule that specifies a recipe for the target need not have any prerequisites. For example, the rule containing the delete command associated with the target 'clean' does not have prerequisites.

The system command(s) (also called recipe) is an action that make carries out. A recipe may have more than one command, either on the same line or each on its own line.

Execution

A Makefile is executed with the make command.

make [options] [target1 target2 ...]

By default, when make looks for the makefile, if a makefile name was not included as a parameter, it tries the following names, in order: makefile and Makefile.[1]

Example

Here is a simple makefile that describes the way an executable file called edit depends on four object files which, in turn, depend on four C source and two header files.

edit : main.o kbd.o command.o display.o 
    cc -o edit main.o kbd.o command.o display.o
 
main.o : main.c defs.h
    cc -c main.c
kbd.o : kbd.c defs.h command.h
    cc -c kbd.c
command.o : command.c defs.h command.h
    cc -c command.c
display.o : display.c defs.h
    cc -c display.c
 
clean :
     rm edit main.o kbd.o command.o display.o

To use this makefile to create the executable file called edit, type: make

To use this makefile to delete the executable file and all the object files from the directory, type: make clean

References