Dark silicon

Dark silicon is a term used in the electronics industry. In the nano-era, transistor scaling and voltage scaling are no longer in line with each other, resulting in the failure of Dennard scaling. This discontinuation of Dennard scaling has led to sharp increases in power densities that hamper powering-on all the transistors simultaneously at the nominal voltage, while keeping the chip temperature in the safe operating range. "Dark Silicon" refers to the amount of silicon that cannot be powered-on at the nominal operating voltage for a given thermal design power (TDP) constraint. According to recent studies, researchers from different groups have projected that, at 8 nm technology nodes, the amount of Dark Silicon may reach up to 50%-80%[1] depending upon the processor architecture, cooling technology, and application workloads. Dark Silicon may be unavoidable even in server workloads with abundance of inherent client request-level parallelism.[2]

Challenges and opportunities

The emergence of Dark Silicon introduces several challenges on the architecture, electronic design automation (EDA), and Hardware-Software co-design communities. For instance, how best to utilize the plethora of transistors (with potentially many dark ones) for designing and managing energy-efficient on-chip many-core systems under peak power and thermal constraints. Architects have initiated several efforts in leveraging the Dark Silicon to design application-specific and accelerator-rich architectures.[3][4][5] Recently, researchers have explored how Dark Silicon exposes new challenges and opportunities for the EDA community.[6] In particular, they have demonstrated the thermal, reliability (soft error and aging), and process variation concerns for Dark Silicon many-core processors.

References

  1. ↑ H. Esmaeilzadeh et al., "Dark silicon and the end of multicore scaling", in 38th International Symposium on Computer Architecture (ISCA), pages 365 –376, 2011.
  2. ↑ N. Hardavellas, M. Ferdman, B. Falsafi, A. Ailamaki, "Toward Dark Silicon in Servers," IEEE Micro, vol. 31, no. 4, pp. 6-15, July/August, 2011.
  3. ↑ G. Venkatesh et al., "Conservation cores: reducing the energy of mature computations", in 15th Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 205–218, 2010.
  4. ↑ J. Cong et al., "Architecture support for accelerator-rich CMPs", in 49th IEEE/ACM/EDAA Design Automation Conference (DAC), 2012.
  5. ↑ M. Lyons et al., "The accelerator store: A shared memory framework for accelerator-based systems", ACM Transactions of Architecture Code Optimizations (TACO), 8(4):48:1–48:22, 2012.
  6. ↑ M. Shafique, S. Garg, D. Marculescu, J. Henkel, "The EDA Challenges in the Dark Silicon Era", in 51st IEEE/ACM/EDAA Design Automation Conference (DAC), 2014.