Wafer-level packaging

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Wafer-level packaging (WLP) is the technology of packaging an integrated circuit while still part of the wafer, in contrast to the more conventional method of slicing the wafer into individual circuits (dice) and then packaging them. WLP is essentially a true chip-scale package (CSP) technology, since the resulting package is practically of the same size as the die.[1] Wafer-level packaging allows integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device from silicon start to customer shipment.

Wafer-level packaging consists of extending the wafer fab processes to include device interconnection and device protection processes. Most other kinds of packaging do wafer dicing first, and then put the individual die in a plastic package and attach the solder bumps. Wafer-level packaging involves attaching the top and bottom outer layers of packaging, and the solder bumps, to integrated circuits while still in the wafer, and then wafer dicing.

There is no single industry-standard method of wafer-level packaging at present.

See also

References

  1. ↑ "Tessera Working WLP, Wafer-Level Optics", Semiconductor International, April 1 2009.

External links

Diode
Transistor
Single row
  • SIP / SIL
Dual row
Quad row
  • LCC
  • PLCC
  • QFN
  • QFP
  • QUIP / QUIL
Grid array
Wafer
Related topics
Note: It's relatively common to find packages that contain other components than their designated ones, such as voltage regulators in transistor packages, etc.
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