Quilt packaging
Quilt Packaging (QP) is a electronic packaging technology that incorporates conductive “nodules” fabricated on the sides of chips. These nodule structures can function as extremely wide bandwidth, low-loss electrical I/O, with sub-micron mechanical chip-to-chip alignment. QP can be implemented in a variety of substrates, including Si, GaAs, SiC, GaN, SiGe, InP, GaSb and more. When utilized for electrical I/O, QP nodules perform as if they were on-chip interconnects even though they run off-chip, having demonstrated around 2 dB of insertion loss across the entire bandwidth from 50 MHz to 220 GHz [1]. QP nodules are lithographically defined and can be fabricated in multiple geometries on the same side of a chip, from digital signal lines at 10 micron pitch, to “tuned” coplanar waveguides to power structures hundreds of microns wide.
QP offers the ability to combine multiple and disparate chip technologies into an array of chips, interconnected along their edges form a "quilt" of chips that act as single, monolithic-like system. QP quilts are packaged as any monolithic IC, and can be combined with other packaging approaches such as bumping, wirebonding, and TSV. Implemented at the wafer level, Quilt Packaging fabrication is very similar to a “via middle” approach and utilizes industry-standard tools and processes.[2]
References
- ↑ P. Fay, D. Kopp, T. Lu, D. Neal, G.H. Bernstein, J.M. Kulick, "Ultrawide Bandwidth Chip-to-Chip Interconnects for III-V MMICS, " IEEE Microwaves and Wireless Components Letters, Vol. PP, Issue 99, November 2013.
- ↑ "Quilt Packaging Concept" http://www.indianaic.com/#!concept/c7bn
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