POWER8

POWER8 is a Power Architecture based superscalar symmetric multiprocessor introduced in August 2013 at the Hot Chips conference. It's available for licensing under the OpenPOWER Foundation which is a first for IBM's highest end processors. IBM have suggested a mid-2014 timeframe for systems based on POWER8 to be available.^[1]

Design

POWER8 is designed to be a massively multithreaded chip, capable of handling 96 hardware threads simultaneously. The chip makes use of very large amounts of on- and off-chip eDRAM caches, and on-chip memory controllers enable very high bandwidth to memory and system I/O. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the POWER7.^[2]

Where previous POWER processors use the GX++ bus for external communication, POWER8 removes this from the design and replaces it with the CAPI port (Coherence Attach Processor Interface) which is layered on top of PCI Express 3.0. The CAPI port is used to connect auxiliary specialized processors such as GPUs, ASICs and FPGAs.<ref name=pcworld">IBM's new Power8 doubles performance of Watson chip</ref>^[3] Units attached to the CAPI bus can use the same memory address space as the CPU. At the 2013 ACM/IEEE Supercomputing Conference, IBM and Nvidia announced an engineering partnership to closely couple POWER8 with Nvidia GPUs in future HPC systems.^[4]

The chip is fabricated on a 22 nm Silicon on insulator (SOI) process using 15 metal layers, and is 650 mm² large.

Centaur

The memory controllers on the POWER8 chips is specified to use either DDR3 or DDR4 bus are designed to be future proof by being a generic memory controller with an external component called Centaur that will act as a memory buffer, L4 cache chip and actual memory controller. The current Centaur chip is using DDR3 memory but a future version can use DDR4 without need to swap the POWER8 chip itself.

The link between the POWER8 chip and the Centaur is a 9.6 GB/s with 40 ns latency. It contains 16 MB of eDRAM which can be used as L4 cache by the processor. Each POWER8 can be linked to up to eight Centaur chips for an aggregated 128 MB L4 cache and 230 GB/s sustained and 410 GB/s peak memory bandwidth in and out of the processor.^[1]

The Centaur chips are fabricated on a similar process as the POWER8.

Specifications

The POWER8 core has 64 KB L1 data and 32 KB L1 instruction caches, and 512 KB SRAM L2 cache on a 64-byte wide bus, twice as wide as its predecessor.^[1] Each core can issue 10 instructions and dispatch 8 each cycle to 16 Execution Units (EU); 2× Fixed-Point Units (FXU), 2× Load-Store Units (LSU), 2× Instruction Fetch Units (IFU), 4× Floating Point Units (FPU), 2× VMX units, 1× Cryptographic Unit, 1× Decimal Floating Unit (DFU), 1× Condition Register Unit (CRU), and 1× Branch Register Unit (BRU).

It has a larger issue queue with 4×16 entries, improved branch predictors and can handle twice as many cache misses. Each core is eight-way hardware multithreaded and can be dynamically and automatically partitioned to have either one, two, four or all eight threads active.^[1] IBM estimates that each core is 1.6 times as fast as the POWER7 in single-threaded operations.

A POWER8 chip has 12 cores and 96 MB eDRAM L3 cache, 8 MB per core. The chip can also utilize an up to 128 MB off-chip eDRAM L4 cache using Centaur companion chips. The on-chip memory controllers can handle 1 TB RAM and 230 GB/s sustained memory bandwidth. The on-board PCI Express controllers can handle 48 GB/s of I/O to other parts of the system.

Licensees

In January 19, 2014, the Suzhou PowerCore Technology Company announced that they will join the OpenPOWER Foundation and license the POWER8 core to design custom-made processors for use in big data and cloud computing applications.^[5][6]

See also

• IBM POWER microprocessors
• OpenPOWER Foundation
• POWER7
• Power Architecture
• PowerPC A2

References

External links

• POWER8 Overview, IBM Power Systems (PDF)