Intel iPSC

The Intel Personal SuperComputer (Intel iPSC) was a product line of parallel computers in the 1980s and 1990s. The iPSC/1 was superseded by the Intel iPSC/2, and then the Intel iPSC/860.

Four-dimensional hypercube topology

iPSC/1

In 1984, Justin Rattner became manager of the Intel Scientific Computers group in Beaverton, Oregon. He hired a team that included mathematician Cleve Moler.^[1] The iPSC used a hypercube of connections between the processors internally inspired by the Caltech Cosmic Cube research project. For that reason, it was configured with nodes numbering with power of two, which correspond to the corners of hypercubes of increasing dimension.^[2]

Intel announced the iPSC/1 in 1985, with 32 to 128 nodes connected with Ethernet into a hypercube. The system was managed by a personal computer of the PC/AT era running Xenix, the "cube manager".^[3] Each node had a 80286 CPU with 80287 math coprocessor, 512K of RAM, and eight Ethernet ports (seven for the hypercube interconnect, and one to talk to the cube manager).^[1]

A message passing interface called NX that was developed by Paul Pierce evolved throughout the life of the iPSC line.^[4] Because only the cube manager had connections to the outside world, developing and debugging applications was difficult.^[5]

The basic models were the iPSC/d5 (five-dimension hypercube with 32 nodes), iPSC/d6 (six dimensions with 64 nodes), and iPSC/d7 (seven dimensions with 128 nodes). Each cabinet had 32 nodes, and prices ranged up to about half a million dollars for the four cabinet iPSC/d7 model.^[1] Extra memory (iPSC-MX) and vector processor (iPSC-VX) models were also available, in the three sizes. A four-dimensional hypercube was also available (iPSC/d4), with 16 nodes.^[6]

iPSC/1 was called the first parallel computer built from commercial off-the-shelf parts.^[7] This allowed it to reach the market about the same time as its competitor from nCUBE, even though the nCUBE project had started earlier. Each iPSC cabinet was (overall) 127 cm x 41 cm x 43 cm. Total computer performance was estimated at 2 MFLOPS. Memory width was 16-bit.

iPSC/2

The Intel iPSC/2 was announced in 1987. It was available in several configurations, the base setup being one cabinet with 16 Intel 80386 processors at 16 MHz, each with 4 MB of memory and a 80387 coprocessor on the same module.^[8] The operating system and user programs were loaded from a management PC. This PC was typically an Intel 301 with a special interface card. Instead of Ethernet, a custom Direct-Connect Module with 8 channels of about 2.8 Mbyte/s data rate each was used for hypercube interconnection.^[8] The custom interconnect hardware resulting in higher cost, but reduced communication delays.^[9] The software in the management processor was called the System Resource Manager instead of "cube manager". The system allows for expansion up to 128 nodes, each with processor and coprocessor.^[10]

The base modules could be upgraded to the SX (Scalar eXtension) version by adding a Weitek 1167 floating point unit.^[11] Another configuration allowed for each processor module to be paired with a VX (Vector eXtension) module with a dedicated multiplication and addition units. This has the downside that the number of available interface card slots is halved. Having multiple cabinets as part of the same iPSC/2 system is necessary to run the maximum number of nodes and allow them to connect to VX modules.^[12]

The nodes of iPSC/2 ran the proprietary NX/2 operating system, while the host machine ran System V or Xenix.^[13] Nodes could be configured like the iPSC/1 without and local disk storage, or use one of the Direct-Connect Module connections with a clustered file system (called concurrent file system at the time).^[12][14] Using both faster node computing elements and the interconnect system improved application performance over the iPSC/1.^[15][16] An estimated 140 iPSC/2 systems were built.^[17]

iPSC/860

Intel announced the iPSC/860 in 1990. The iPSC/860 consisted of up to 128 processing elements connected in a hypercube, each element consisting of an Intel i860 at 40–50 MHz or Intel 80386 microprocessor.^[18] Memory per node was increased to 8 MB and a similar Direct-Connect Module was used, which limited the size to 128 nodes.^[19]

One customer was the Oak Ridge National Laboratory.^[18] The performance of the iPSC/860 was analyzed in several research projects.^[20][21] The iPSC line was superseded by a research project called the Touchstone Delta at the California Institute of Technology which evolved into the Intel Paragon.

References

1. ↑ 1.0 1.1 1.2 Cleve Moler (October 28, 2013). "The Intel Hypercube, part 1". Retrieved November 4, 2013. 
2. ↑ "The Personal SuperComputer". Computer History Museum. Retrieved November 4, 2013. 
3. ↑ Paul R. Pierce. "Intel iPSC/1". Archived from the original on June 3, 2013. Retrieved November 4, 2013. 
4. ↑ Paul Pierce (April 1994). "The NX message passing interface". Parallel Computing (Elsevier Science Publishers) 20 (4): 1285–1302. doi:10.1016/0167-8191(94)90023-X. 
5. ↑ Martin J. Schedlbauer (1989). "An I/O management system for the iPSC/1 hypercube". Proceedings of the 17th conference on ACM Annual Computer Science Conference: 400. doi:10.1145/75427.1030220. 
6. ↑ http://delivery.acm.org/10.1145/70000/63074/p1207-orcutt.pdf[]
7. ↑ Paul R. Pierce. "Other Artifacts in the Collection". Archived from the original on June 3, 2013. Retrieved November 4, 2013. 
8. ↑ 8.0 8.1 "Intel iPSC/2 (Rubik)". Computer Museum. Katholieke Universiteit Leuven. Retrieved November 4, 2013. 
9. ↑ Philip J. Hatcher and Michael Jay Quinn (1991). Data-parallel Programming on MIMD Computers. MIT Press. p. 7. ISBN 9780262082051. 
10. ↑ P. Pal Chauddhuri (2008). Computer Organization and Design. PHI Learning. p. 826. ISBN 9788120335110. 
11. ↑ Si. Pi Ravikumār (1996). Parallel Methods for VLSI Layout Design. Greenwood Publishing Group. p. 183. ISBN 9780893918286. 
12. ↑ 12.0 12.1 Jack Dongarra and Iain S. Duff (1991). "Advanced Architecture Computers". In Hojjat Adeli. Supercomputing in Engineering Analysis. CRC Press. pp. 51–54. ISBN 9780893918286. 
13. ↑ Paul Pierce (1988). "The NX/2 operating system". Proceedings of the third conference on Hypercube concurrent computers and applications (ACM): 384–390. doi:10.1145/62297.62341. ISBN 0-89791-278-0. 
14. ↑ James C. French, Terrence W. Pratt and Mriganka Das (May 1991). "Performance measurement of a parallel Input/Output system for the Intel iPSC/2 Hypercube". Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems (ACM): 178–187. doi:10.1145/107971.107990. ISBN 0-89791-392-2. 
15. ↑ S. Arshi, R. Asbury, J. Brandenburg and D. Scott (1988). "Application performance improvement on the iPSC/2 computer". Proceedings of the third conference on Hypercube concurrent computers and applications (ACM): 149–154. doi:10.1145/62297.62316. ISBN 0-89791-278-0. 
16. ↑ Luc Bomans and Dirk Roose (September 1989). "Benchmarking the iPSC/2 hypercube multiprocessor". Concurrency: Practice and Experience (John Wiley & Sons) 1 (1): 3–18. doi:10.1002/cpe.4330010103. 
17. ↑ Gilbert Kalb, Robert Moxley, ed. (1992). "Commercially Available Systems". Massively Parallel, Optical, and Neural Computing in the United States. IOS Press. pp. 17–18. ISBN 9781611971507. 
18. ↑ 18.0 18.1 Siddharthan Ramachandramurthi (1996). "iPSC/860 Guide". Computational Science Education Project at Oak Ridge National Laboratory. Retrieved November 4, 2013. 
19. ↑ V. Venkatakrishnan (1991). "Parallel Implicit Methods for Aerodynamic Applications on Unstructured Grids". In David E. Keyes, Y. Saad, Donald G. Truhlar. Domain-based Parallelism and Problem Decomposition Methods in Computational Science and Engineering. SIAM. p. 66. ISBN 9781611971507. 
20. ↑ Rudolf Berrendorf and Jukka Helin (May 1992). "Evaluating the basic performance of the Intel iPSC/860 parallel computer". Concurrency: Practice and Experience (John Wiley & Sons) 4 (3): 223–240. doi:10.1002/cpe.4330040303. 
21. ↑ T. H. Dunigan (December 1991). "Performance of the Intel iPSC/860 and Ncube 6400 hypercubes". Parallel Computing (Elsevier Science Publishers) 17 (10–11): 1285–1302. doi:10.1016/S0167-8191(05)80039-0.