F16C

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The F16C (previously/informally known as CVT16) instruction set is x86 instruction set architecture extension which provide support for converting between half-precision and standard IEEE single-precision floating-point formats.

History

The CVT16 instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set.

CVT16 is a revision of part of the SSE5 instruction set proposal announced on August 30, 2007, which is supplemented by the XOP and FMA4 instruction sets. This revision makes the binary coding of the proposed new instructions more compatible with Intel's AVX instruction extensions, while the functionality of the instructions is unchanged.

In recent documents, the name F16C is formally used in both Intel and AMD x86-64 architecture specifications.

Technical Information

There are variants that convert 4 floating-point values in an XMM register or 8 floating-point values in a YMM register.

The instructions are abbreviations for "vector convert packed half to packed single" and vice-versa:

VCVTPH2PS xmmreg,xmmrm64 Convert 4 half-precision floating point values in memory or the bottom half of an XMM register to 4 single-precision floating-point values in an XMM register.
VCVTPH2PS ymmreg,xmmrm128 Convert 8 half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to 8 single-precision floating-point values in a YMM register.
VCVTPS2PH xmmrm64,xmmreg,imm8 Convert 4 half-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register.
VCVTPS2PH xmmrm128,ymmreg,imm8 Convert 8 half-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register.

The 8-bit immediate argument to VCVTPS2PH selects the rounding mode. Values 0–4 select nearest, down, up, truncate, and the mode set in MXCSR.RC.

Support for these instructions is indicated by bit 29 of ECX after CPUID with EAX=1.

External links

AMD64 Architecture Programmer's Manual Volume 1
AMD64 Architecture Programmer's Manual Volume 2
AMD64 Architecture Programmer's Manual Volume 3
AMD64 Architecture Programmer's Manual Volume 4
AMD64 Architecture Programmer's Manual Volume 5
IA32 Architectures Software Developer Manual

v t e Multimedia extensions

RISC	PA-RISC Multimedia Acceleration eXtensions (MAX) SPARC Visual Instruction Set (VIS) MIPS MDMX MIPS-3D Alpha Motion Video Instructions (MVI) Power Architecture AltiVec ARM NEON

x86 (current)	MMX (1996) 3DNow! (1998) Streaming SIMD Extensions (SSE) (1999) SSE2 (2001) SSE3 (2004) Supplemental SSE3 (SSSE3) (2006) SSE4 (2006) SSE5 ~~(2007)~~ Advanced Encryption Standard (AES) (2008) Advanced Vector Extensions (AVX) (2008) F16C (2009 (AMD), 2011 (Intel)) XOP (2009) FMA instructions (FMA4: 2011, FMA3: 2012 (AMD), 2013 (Intel))

x86 (planned)

x86 : Instructions (Year Introduced); Italics = AMD exclusive; ~~Year~~ = Superseded

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