Duron
 AMD Duron "Spitfire" 600MHz CPU | |
| Produced | From mid 2000 to 2004 |
|---|---|
| Common manufacturer(s) |
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| Max. CPU clock rate | 600 MHz to 1.8 GHz |
| FSB speeds | 200 MT/s to 266 MT/s |
| Min. feature size | 0.18µm to 0.13µm |
| Instruction set | x86 |
| Socket(s) | |
| Core name(s) |
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The AMD Duron is a x86-compatible microprocessor that was manufactured by AMD. It was released on June 19, 2000 as a low-cost alternative to AMD's own Athlon processor and the Pentium III and Celeron processor lines from rival Intel. The Duron was discontinued in 2004 and succeeded by the Sempron.
Development
The Duron was pin-compatible with the Athlon and carried all of the computational resources from it, operating on the same motherboards in most cases. The original Duron ran with a 100MHz/200MHz DDR FSB (Front Side Bus), the same speed as the first generation of Socket A Athlons. However, with the introduction of motherboard chipsets that could offer FSB speeds of 133MHz(266DDR), AMD introduced Athlons (running at a base speed of 1GHz) that accommodated them, while leaving the Duron on a 100MHz FSB in order to better differentiate the product. Later Durons supported a 133 MHz bus (FSB 266) while Athlon XP ran at 166/200 MHz FSB (FSB 333/400). The original Duron, using the "Spitfire" core, was manufactured in 2000 and 2001 at speeds ranging from 600 to 950 MHz. It was based on the 180 nm "Thunderbird" Athlon core. The second-generation Duron, the "Morgan" core, was sold in speed grades between 900 and 1300 MHz, and was based on the 180 nm "Palomino" Athlon XP core. As a result, it featured a few important enhancements namely full Intel SSE support, enlarged TLBs, hardware data prefetch, and an integrated thermal diode. Like the "Palomino" core, "Morgan" was also expected to reduce the core heat dissipation, however in "Morgan"'s case this did not happen due to its increased core voltage. The final generation Duron was called "Applebred", sometimes called "Appalbred", and was based on the "Appaloosa" Duron along with the 130 nm "Thoroughbred" Athlon XP. "Appaloosa" was never officially announced but it did see very limited circulation.
Duron's biggest difference from Athlon was its reduction in cache size to 64 KB, in contrast to the 256 KB or even 512 KB of Athlon. This was a relatively tiny amount of L2 cache, even smaller than the 128 KB L2 on Intel's Celeron. However, the K7-architecture enjoyed one of the largest L1 caches, at 128 KB (split 64+64 KB). And, with the arrival of the socketed Athlon/Duron chips, AMD switched to an exclusive cache design which did not mirror data between the L1 and L2 like the inclusive cache used on the Slot A K7, a critical feature in a low-cache situation. An exclusive design greatly favors L1 cache as the primary caching resource, while the slower L2 cache stores victim or copy-back cache blocks to be written back to main memory (LRU). The L2 cache essentially acts as an overflow from the L1 cache. Because of the lack of duplication between caches, Duron can be said to have 192 KB cache on board, whereas an inclusive chip such as Athlon Slot-A, with 512 KB L2, would only have, in practice, 512 KB total (640K-128K). Celeron was in the same boat with its inclusive cache for a total of 128 KB (160K-32K).
Consequently, the post-Slot-A K7-architecture was less sensitive to L2 cache size. This reduced reliance upon L2 cache also allowed AMD to make their L2 cache higher latency and lower bandwidth without significant performance loss, which lessened processor complexity and allowed better manufacturing yields. AMD's Duron "Spitfire" CPU was only roughly 10% slower than its big brother, Athlon "Thunderbird".
Duron was often a favorite of computer builders looking for performance while on a tight budget. Perhaps most notably, in 2003 the "Applebred" Duron was available in 1.4 GHz, 1.6 GHz and 1.8 GHz forms, all on a 133 MHz (FSB 266) bus by default. Enthusiast groups quickly discovered these Durons to be rebadged Thoroughbred A/B cores with some cache disabled (and perhaps defective). With a basic chip configuration modification, it was found that "Applebred" could be turned into "Thoroughbred B" Athlon XPs, with full 256KB cache, with a very high success rate. However, this was only possible for a period of approximately 4 weeks, as shortly after the Applebred was released, AMD changed the chip configuration method to one that was not changeable.
Duron core data
Spitfire (Model 3, 180 nm)
- L1-Cache: 64 + 64 KB (Data + Instructions)
- L2-Cache: 64 KB, fullspeed
- MMX, Extended MMX, 3DNow!, Extended 3DNow!
- Socket A (EV6)
- Front side bus: 100 MHz (200 MT/s)
- VCore: 1.50 V - 1.60 V
- First release: June 19, 2000
- Clockrate: 600 MHz - 950 MHz
Morgan (Model 7, 180 nm)
- L1-Cache: 64 + 64 KB (Data + Instructions)
- L2-Cache: 64 KB, fullspeed
- MMX, Extended MMX, 3DNow!, Extended 3DNow!, SSE
- Socket A (EV6)
- Front side bus: 100 MHz (200 MT/s)
- VCore: 1.75 V
- First release: August 20, 2001
- Clockrate: 900 MHz - 1300 MHz
Applebred (Model 8, 130 nm)
- L1-Cache: 64 + 64 KB (Data + Instructions)
- L2-Cache: 64 KB, fullspeed
- MMX, Extended MMX, 3DNow!, Extended 3DNow!, SSE
- Socket A (EV6)
- Front side bus: 133 MHz (266 MT/s)
- VCore: 1.50 V
- First release: August 21, 2003
- Clockrate: 1400, 1600, 1800 MHz
See also
List of AMD Duron microprocessors
References
- "AMD Duron (64 KB integrated Level 2 cache)" by Anthony Barrett, Processor Emporium, retrieved January 13, 2006
- "cpu-museum.de New additions to the museum (Appalbred)", by Christian "Grampa", January 7, 2004, retrieved January 9, 2006, Archived at the Wayback Machine (archived July 18, 2011)
- "IA-32 implementation AMD K7 (inclusive on Slot A)" by Sandpile.org, retrieved January 9, 2006
- "Press Release: AMD Athlon Processor Performance-Enhancing Cache Memory" by AMD, June 4, 2000, retrieved January 13, 2006
- ADSK v ODA
External links
- Budget CPU Shootout - Popular hardware review website Anandtech compares low priced CPUs
- cpu-collection.de AMD Duron processor images and descriptions
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