The Western Design Center WDC 65C02 microprocessor is an upgraded CMOS version of the popular NMOS-based MOS Technology 6502 8-bit CPU — the CMOS redesign being made by Bill Mensch of the Western Design Center (WDC). Over various periods of time, the 65C02 has been second-sourced by NCR, GTE, Rockwell, Synertek and Sanyo.
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The W65C02S is Western Design Center's version of the 65C02 microprocessor. The "S" designation indicates that the part has a fully static core which allows the primary clock to be slowed down indefinitely or fully stopped in either the high or low state.
The W65C02S is a low-power general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The variable length instruction set and manually optimized core size are intended to make the W65C02S well suited for low power system-on-chip (SoC) designs.
WDC makes a Verilog hardware description model available for designing the 65C02 core into ASICs and FPGAs. As is common in the semiconductor industry, the company also provides a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.
The WDC 65C02 can run at any supply voltage (VDD) between 1.8 and 5 volts (±5%). There are not different chips for different logic supply voltages. The data sheet shows graphs of how various parameters (e.g. IDD, Fmax) change with VDD, and tables showing their values at commonly used VDD values (1.8, 2.5, 3.0, 3.3, 5.0 V ±5%).
The WDC6502 data sheet table 6.3 shows AC characteristics at 5V/14MHz, 3.3V/8MHz, 3V/8MHz, 2.5V/4MHz, and 1.8V/2MHz. This may be left over from an earlier data sheet, because the graph in figure 6.2 indicates that typical devices run over 18 MHz at 4V, and 6MHz at 1.8V.
The -14 suffix should not be taken as a 14 MHz hard limit. The WDC6502 may well run at convenient clocks such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818.. MHz (NTSC colour carrier × 4), 14.75 MHz (PAL square pixels), 14.7456 (baud rate crystal), 16 MHz and so on. However, the minimum VDD value rises accordingly.
Bill Mensch pointed out that Fmax depends on off-chip factors such as the capacitive load on the pins. Minimising load by using short signal tracks and fewest devices helps raise Fmax. The PLCC package has less pin-to-pin capacitance than the DIP-40 package.
The 65C02 shares its predecessor's 8-bit instruction set architecture and 16-bit memory addressing, but adds a number of improvements and documented opcodes, the most useful being instructions that can push or pull the X and Y index registers to/from the stack. Undefined opcodes have been converted into NOPs, although of varying instruction lengths.
Significantly, the defective "indirect jump page wrap" instruction (JMP (<ADDR>), where <ADDR> straddles a memory page boundary) has been fixed, eliminating a constant source of trouble for unwary assembly language programmers. This instruction has also been enhanced with .X register indexing, making it possible to code JMP (<ADDR>,X), enabling the development of a simple jump table management methodology.
Some variants of the 65C02 (including the WDC W65C02S and the Rockwell R65C00 family) feature individual bit manipulation operations (RMB, SMB, BBR and BBS). The 65SC02 was also available, which lacked these operations.
Other problems with the 6502, fixed in the 65C02, relate to its program status register, which contains eight system flags. Some flags are set or reset under program control. Others reflect the status of the machine after arithmetic or bit manipulation instructions.
| N | -- | Negative result |
| V | -- | Sign bit overflow |
| 1 | -- | Undefined (always set) |
| B | -- | Break flag (set by BRK instruction) |
| D | -- | Decimal mode enabled |
| I | -- | IRQ disabled |
| Z | -- | Zero result |
| C | -- | Arithmetic carry (borrow) |
In all NMOS logic forms of the 6502, the decimal flag (D flag) is not initialized to a known state following reset or when an interrupt is processed, which may lead to arbitrary behavior. This forces 6502 programmers to use the CLD instruction early in the reset handler code (it is generally the second instruction executed after SEI), as well as in the front end of the interrupt handler. The 65C02 addresses these problems by causing the D flag to be cleared at reset or upon receipt of an interrupt (after the status register is pushed onto the stack).
Also, in NMOS 6502s, the N flag is invalid when the processor is operating in decimal mode. The 65C02 fixes this problem (at the cost of an additional clock cycle), and thus increases the usefulness of decimal mode.
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