| Developer(s) | Wilson Snyder |
|---|---|
| Development status | Active |
| Operating system | Cross-platform |
| Type | Simulator |
| License | Artistic + GNU General Lesser Public License |
| Website | http://www.veripool.org/verilator/ |
Verilator is a free and open source software tool which converts Verilog (a hardware description language) to a cycle accurate behavioral model in C++ or SystemC. It is restricted to modeling the synthesizable subset of Verilog and the generated models are cycle accurate, 2-state, with synthesis (zero delay) semantics. As a consequence the models typically offer higher performance than the more widely used event driven simulators, which can process the entire Verilog language and model behavior within the clock cycle. Verilator is now used within academic research, open source projects and for commercial semiconductor development. It is part of the growing body of free EDA software.
Contents |
Verilator has seen its widest adoption in the academic and open source communities. The semiconductor industry has been more cautious in its adoption of an open source tool, and has the financial wherewithal to use commercial alternatives such as Model Studio from Carbon Design Systems and VTOC from ARC International.
Researchers have used Verilator to develop new co-simulation environments,[2] as part of general ASIC and FPGA design flows [3][4] and in performance and power analysis.[5] Verilator is also a popular tool for student dissertations, for example.[6]
Verilator is an open source tool, and has in turn been adopted by a number of other projects. The Fedora Electronic Lab [6] has adopted Verilator as part of its open source design flow for Fedora 11. The OpenRISC architecture from OpenCores includes a cycle accurate reference model, generated from Verilog using Verilator. A recent paper [7] described how the regression test suite for GCC could be run against a Verilator model of the OpenRISC 1200 as a way of detecting errors in the Verilog RTL implementation.
Commercially, Philips Semiconductors (now NXP) have led the way.[8] Their use of Verilator is becoming more widespread, for example within application notes.[9] More recently Art of Silicon have described their use of Verilator on a farm of Linux processors as a route to faster regression testing of their commercial designs.[10][11] The current maintainer of Verilator identified [12] 27 companies and universities who had reported use of Verilator or contributed to its development, including Intel, ARM, CSR, Broadcom, Raytheon, Infineon, Imperial College London and Embecosm.
Verilator's user manual provides a short history.[13] The tool originated in 1994 with a team led by Paul Wasson at the Core Logic Group at Digital Equipment Corporation (DEC). It was used to convert Verilog code to C for co-simulation with a C based CPU model of the Alpha processor. During the mid-1990s Duane Galbi took over responsibility for development and the technology was adopted by other groups in DEC. In 1998 DEC released the source code.
Since 2001 the technology has been developed by Wilson Snyder and others as part of the Veripool open source project. A SystemC mode was added and the tool rewritten from scratch in C++, leading to an increase in performance.
Verilator converts synthesizable Verilog to C++ or SystemC. It can handle all versions of Verilog and also some SystemVerilog and Sugar/PSL assertions. The approach is closer to synthesis than event driven simulation. The entire design is flattened (that is all modules are expanded, to create one module). Static analysis is used to eliminate wires and schedule all processes at model generation time. Since this is a cycle accurate model, all intra-cycle delays are ignored. A C++ class is generated with a function which will take 2-state values on input ports and advance them to values on output ports at the next clock edge.
SystemC is supported by providing a wrapper class using SystemC ports, and with sensitivity to the clock(s), which will drive the ports of the underlying C++ model.
Verilator converts synthesizable Verilog to C++, while C++ library could be compiled into MEX file using MATLAB interface to C++. This is how Verilog designs can be directly simulated from MATLAB. Using compiled C++ models with MATLAB is faster than using co-simulation interface with separate HDL simulator. There is an open-source project vmodel that compiles Verilog into MEX file using Verilator, and provides a set of functions for model simulation from MATLAB.