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The PowerPC 400 family is a line of 32-bit embedded RISC processor cores built using Power Architecture technology. The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers.
Applied Micro Circuits Corporation (AMCC) bought assets concerning the 400 family cores from IBM in April 2004 for $227 million, and they now market the processors under their own name. IBM continues evolving the cores while supplying design and foundry services around the cores. Several cores are also available for licensing by OEMs from IBM and Synopsys.
Contents |
| Name | Pipeline stages |
|---|---|
| PowerPC 401 | 3 |
| PowerPC 405 | 5 |
| PowerPC 440 | 7 |
| PowerPC 470 | 9 |
Introduced in 1994, the PowerPC 403 was one of the first PowerPC processors. It was the first one targeted strictly to the embedded market. Compared to the other PowerPC processors of the era (PowerPC 601, PowerPC 603 and PowerPC 604), it was at the very low end, lacking a memory management unit (MMU) or floating point unit (FPU), for instance. The core was offered for custom chips and in pre packaged versions, including versions with MMU, speeds ranging from 20 to 80 MHz.
The PowerPC 403 is used in, among other appliances, thin clients, set-top boxes, RAID-controllers, network switches and printers. The first TiVo used a 54 MHz PowerPC 403GCX.
AMCC acquired the design of 403 from IBM in 2004, but have chosen not to market it, instead focusing on the 405 and 440 cores.
While the 403 was popular, it was also too high performance and too costly for some applications, so in 1996 IBM released a bare bones PowerPC core, called PowerPC 401. It has a single issue, three-stage pipeline, with no MMU or DMA and only 2 KB instruction and 1 KB data L1 caches. The design contained just 85,000 transistors in all and operated at up to 100 MHz, drawing only 0.1 W or less. Applications using the 401 core range from set-top boxes and telecom switches to printers and fax machines.[1][2]
The PowerPC 405 was released in 1998 and was designed for price or performance sensitive low-end embedded system-on-a-chip (SoC) designs. It has a five-stage pipeline, separate 16 KB instruction and data L1 caches, a CoreConnect bus, an Auxiliary Processing Unit (APU) interface for expandability and supports clock rates exceeding 400 MHz. The 405 core adheres to the current Power ISA v.2.03 using the Book III-E specification. Both AMCC and IBM are developing and marketing processors using 405 cores. IBM and Synopsys also offers a fully synthesizable core. IBM has announced plans to make the specifications of the PowerPC 405 core freely available to the academic and research community.[3]
PowerPC 405 based applications includes digital cameras, modems, set-top boxes (IBM's STB04xxx processors[4]), cellphones, GPS-devices, printers, fax machines, network cards, storage devices and service processors for servers. Up to two 405 cores are used in Xilinx Virtex-II Pro and Virtex-4 FPGAs. In 2004 Hifn bought IBM's PowerNP network processors that uses 405 cores.[5][6][7][8]
The Chinese company Culturecom uses a 405 core for its V-Dragon processor which powers Linux terminals and set-top-boxes. The V-Dragon processor includes the Multilingual Character Generation Engine (MCGE) that processes and generates Chinese characters directly in the CPU.[9]
AppliedMicro has a series of system on a chip products based on PowerPC 405 core, under a new name: APM801xx. These are the most energy efficient Power Architecture products to date (Fall 2010), and supports frequencies up to 800 MHz at ~1 W, or 0.3 W idling. Made to support a wide range of applications from networking, to storage and media devices.[10]
Introduced in 1999, the PowerPC 440 was the first PowerPC core from IBM to include the Book E extension to the PowerPC specification. It also included the CoreConnect bus technology designed to be the interface between the parts inside a PowerPC based system-on-a-chip (SoC) device.
It is a high performance core with separate 32 kB instruction and data L1 caches, a seven-stage pipeline, supporting speeds up to 800 MHz and L2 cache up to 256 kB. The core lacks a floating point unit (FPU) but it has an associated four-stage FPU that can be included using the APU (Auxiliary Processing Unit) interface. The 440 core adheres to the current Power ISA v.2.03 using the Book III-E specification.
Xilinx currently incorporates one or two cores (depending on the member of the family) into the Virtex-5 FXT FPGA.
Both AMCC and IBM are developing and marketing stand alone processors using 440 cores. IBM and Synopsys also offers fully synthesized cores.
Broad Reach Engineering has used the IBM 440 synthesized core to build a radiation hardened embedded SOC that includes various peripherals (2 ethernet MACs, PCI, memory controllers, DMA controllers, EDAC, SIO), 32kB L1 cache, and 256kB L2 cache. This device was built using the Honeywell HX5000 rad hard process at 150nm. The BRE440 runs at clock speeds ranging from 10's of MHz up to 150MHz.
QCDOC is a custom supercomputer built to solve small but extremely computationally demanding problems in quantum physics. It uses custom 440-based ASICs to obtain a peak performance of approximately 10 TFLOPS.
Dual 440 cores are used in the processors powering IBM's Blue Gene/L supercomputer which until June 2008 ranked number one on the list of the top 500 supercomputers around the world, with a peak performance of nearly 500 teraFLOPS in 2008.
The 440 core is also used in the Cray XT3, XT4 and XT5 supercomputers, where its SeaStar, SeaStar2 and SeaStar2+ communication processors closely couples HyperTransport memory interface with routing to other nodes in supercomputer clusters. The SeaStar device provides a 6.4 GB/s connection to the Opteron based processors across HyperTransport (together making a processing element, PE), as well as six 7.6 GB/s links to neighboring PEs. SeaStar2+ offers 9.6 GB/s intra-node bandwidth and error correcting functionality to intercept errors en-route between computing nodes.
The PowerPC 460EX and 460GT from AMCC are, despite their name, processors with the 440 core. They are available at 0.6 to 1.2 GHz and have integrated controllers for DDR or DDR2 SDRAM, USB 2.0, PCIe, SATA, and Gigabit Ethernet.
Intrinsity designed the now defunct Titan core for AppliedMicro from the ground up using the PowerPC 440 core spec. AppliedMicro used the Titan core in their APM832xx family high performance system on a chip products but these parts never came to market.
In its Virtex-5 FXT FPGA product line, Xilinx embeds up to two PPC440 cores. The embedded PPC440 has a maximum frequency of 550 MHz, and connects to the surrounding FPGA-fabric through a special crossbar switch, increasing the Virtex-5 FXT family's system performance over 2.6 times compared to the Virtex-4 FX family's embedded PPC405.
The Acalis CPU872 is a highly specialized Security SoC chip built by CPU Tech. It is designed for highly sensitive and mission critical systems such as military applications. It has provisions to prevent tampering and reverse engineering and is manufactured at IBM's highly secure Trusted Foundry. It has embedded DRAM, dual 440 cores with dual precision FPUs and auxiliary computing units providing acceleration and protection for communications, complex algorithms and synchronization between cores.[11]
The processing core of the Blue Gene/P supercomputer designed and manufactured by IBM. It is very similar to the PowerPC 440 but few details are disclosed.
The Blue Gene/P processor consists of four PowerPC 450 cores running at 850 MHz reaching 13.6 gigaflops in total. IBM is claiming very power efficient design compared to other supercomputer processors.[12]
Introduced in 2006, the 460 cores are similar to the 440 but reach 1.4 GHz, are developed with multi-core applications in mind and have 24 additional digital signal processing (DSP) instructions. The cores are designed to be low-power but high performance and the 464-H90 is expected to draw only 0.53 W at 1 GHz. The 460 core adheres to Power ISA v.2.03 using the Book III-E specification.
The 470 embedded and customizable core, adhering to the Power ISA v2.05 Book III-E, was designed by IBM together with LSI and implemented in the PowerPC 476FP in 2009.[16] The 476FP core has 32/32 kB L1 cache, dual integer units and a SIMD capable double precision FPU that handles DSP instructions. Emitting 1.6 W at 1.6 GHz on a 45 nm fabrication process. The 9 stage out of order, 5-issue pipeline handles speeds up to 2 GHz, supports the PLB6 bus, up to 1 MB L2 cache and up to 16 cores in SMP configurations.