Massbus
The Massbus was a high-performance computer input/output bus designed in the 1970s by the Digital Equipment Corporation of Maynard, Massachusetts.
The bus was used by Digital to interconnect its highest-performance computers with magnetic disk and magnetic tape storage equipment. The use of a common bus allowed the PDP-10, PDP-11, and VAX computer families to share a common set of peripherals. An additional business objective was to provide a subsystem entry price well below that of IBM storage subsystems which used large and expensive controllers that were unique to each storage technology and optimized for connecting large numbers of storage devices.
Logical implementation
The bus was logically implemented as two separate sections:
- An asynchronous control bus used to access memory-mapped I/O registers in the individual storage devices, and
- A high-speed, synchronous data bus that was used to carry the actual data transfers between the storage devices and the host bus adapter. The data bus was 18 bits wide plus parity. 16 bits were used for PDP-11 and VAX systems, 18 bits for DEC-10s.
- Multiple devices of different types could transmit data over the shared data path. However, this was never supported by DEC operating systems.
- Static dual port was also provided to permit failover or manual switching of storage devices to another CPU.
Massbus storage devices each contained their own autonomous controller units, allowing fully overlapped operation of multiple storage units connected to a single Massbus. The interface between the computer and the Massbus was basically a pass-through device that allowed connection of the common Massbus to the individual computer's internal bus (whether PDP-10 memory bus, Unibus, PDP-11/70 cache bus, or VAX Synchronous Backplane Interconnect). Whenever a storage controller had a data transfer ready, it arbitrated for the use of the Massbus's synchronous data channel.
Physical implementation
The bus was physically implemented in two forms:
- Shielded, controlled-impedance, flat, grey BC06R cables with Berg-styled IDC connectors at each end. Three cables operating in parallel were required to carry all of the Massbus signals.
- Single large, round, heavily shielded cables with ZIF connectors at each end.
- All signals were full differential, and the data bus cycle was 1 microsecond.
The less-expensive flat grey cables were used within shielded equipment enclosures while the round cables were used to connect the enclosures. Transition headers allowed switching freely between the two types of cables and a single Massbus could be daisy-chained between the controller and up to eight mass storage devices. A very heavy ground conductor (wire) also usually joined the equipment.
Massbus peripherals
Disk: (capacities noted are raw, not formatted)
- RM02 80MB, CDC 9762 pack-loaded disk drives, CDC unique disks spin at 2400 RPM
- RM03 80MB, CDC 9762 pack-loaded disk drives, CDC unique disks spin at 3600 RPM
Note the RM02 uses a different drive pulley to slow the disk transfers to a level compatible with a Unibus based PDP11. The RM03 spun at full speed, and was supported on the pdp11/70 and larger systems. Curiously enough the DECSYSTEM 2020 could support an RM03 with its Unibus-based interface due to a highly buffered Unibus-to-memory interface.
- RM05 300MB CDC 9766 pack-loaded disk drives, CDC unique
- RP04 100 MB ISS/Sperry Univac pack-loaded disk drive, IBM 3330 type
- RP05/RP06 100/200 MB Memorex 677-51/677-01 pack-loaded disk drive IBM 3330 type
- RP07 500MB ISS/Sperry Univac non-removable disks IBM 3350 type
- RS03 1MB (formatted) very fast fixed-head disk drives, DEC proprietary plated disk
- RS04 2MB (formatted) very fast fixed-head disk drives, DEC proprietary plated disk
Tape:
- TU16 1600bpi
- TU45 1600bpi
- TU77 1600bpi
- TU78 6250 GCR
Analog I/O
- DR01 Unibus size analog I/O board that connected to the RH20 Massbus controller on a PDP-10
Massbus CPU interfaces
- RH10—To the PDP-10's memory bus
- RH11—To the PDP-11's Unibus
- RH11C—to the KS10's (DECSYSTEM 2020) Unibus
- RH20—To the PDP-10 KL10 CPU (DECsystem 109x, DECSYSTEM-2040/2050/206x) channel bus
- RH70—To the PDP-11/70's Cache Bus
- RH750—To the VAX-11/75x bus
- RH780—To the VAX-11/78x, VAX 86xx SBI (Synchronous Backplane Interconnect) bus
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Note: interfaces are listed in speed ascending order (roughly), the interface at the end of each section should be the fastest
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