MCST-R1000

MCST R1000
MCST R1000 FPGA prototype
Produced	TBD^[1]
Designed by	MCST
Common manufacturer(s)	TSMC
Max. CPU clock rate	750 MHz to 1 GHz
FSB speeds	2 Gbps
Min. feature size	100 mm²
Instruction set	SPARC V9
Cores	4
L1 cache	48 KB
L2 cache	1.5 MB
Application	Embedded
Predecessor	MCST-R500S

Package(s)	FPGA

The MCST R1000 (Russian: МЦСТ R1000) is a 64-bit microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC.^[2]

During development this microprocessor was designated as MCST-4R.^[1]

MCST R1000 Highlights

implements the SPARC V9 instruction set architecture (ISA)
quad-core
core specifications:
- in-order, dual-issue superscalar
- 7-stage integer pipeline
- 9-stage floating-point pipeline
- VIS extensions
- Multiply–accumulate unit
- 16 KB L1 instruction cache (parity protection)
- 32 KB L1 data cache (parity protection)
- size 7.6 mm²
shared 2MB L2 cache (ECC protection)
integrated memory controller
integrated ccNUMA controller
1 GHz clock rate
90 nm process
die size 115 mm²
~150 million transistors
power consumption 15W

References

^ ^a ^b "Участие ЗАО «МЦСТ» и ОАО «ИНЭУМ им.И.С.Брука» в международной выставке “ChipExpo – 2011” (итоги участия)" (in Russian), Новости, MCST, http://www.mcst.ru/news.shtml#111028, retrieved 2011-12-06
^ (in Russian) Система на кристалле «МЦСТ-4R», MCST, http://www.mcst.ru/b_22-23.shtml, retrieved 2011-11-18

List of Russian microprocessors

Manufacturer

Instruction set

MCST

Elbrus, x86	Elbrus Elbrus-S Elbrus-2S+

SPARC	MCST-R150 MCST-R500 MCST-R500S MCST-R1000

ELVEES

MIPS	Multicore NVCom-01

NIISI

MIPS	KOMDIV-32 KOMDIV-64