A MOS 6502 processor in a DIP-40 plastic package. The four-digit date code indicates it was made 45th week of 1985 |
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| Produced | 1975 |
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| Max. CPU clock rate | 1 MHz to 2 MHz |
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The MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle and Bill Mensch for MOS Technology in 1975. When it was introduced, it was the least expensive full-featured microprocessor on the market by a considerable margin, costing less than one-sixth the price of competing designs from larger companies such as Motorola and Intel. It was nevertheless fully comparable with them and, along with the Zilog Z80, sparked a series of computer projects that would eventually result in the home computer revolution of the 1980s. The 6502 design was originally second-sourced by Rockwell and Synertek and later licensed to a number of companies. Soon after the 6502's introduction, MOS Technology was bought outright by Commodore International, who continued to sell the chip to other manufacturers.
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The 6502 was designed primarily by the same engineering team that had designed the Motorola 6800. One of the designers, Chuck Peddle, traveled around with the 6800 to introduce it to potential industrial customers. At the time it was targeted at the embedded market, and although their presentations sparked interest, the price, at about US$300, was simply too high to be widely used. When he asked what sort of price would make the product useful, they settled on US$25. Peddle returned to Motorola and proposed producing a low-cost product to attack this market, but found that management was uninterested; the 6800 was generating nice profits, there seemed to be no reason to change their sales efforts.[1][2]
Undaunted, Peddle started working on such a design on his own. The new design was similar to the 6800 in that it also used a small number of processor registers with a single accumulator. The new design fixed one of the 6800's greatest problems, and allowed the accumulator and index registers to be used together as inputs and offsets. Other additions included the ability to perform binary coded decimal arithmetic and on-chip clock generation; only a single external clock signal was needed, and the new CPU could itself supply clock signals to other chips in a system, eliminating the need for a number of external components.
As the effort continued, the design team grew increasingly unhappy with management's lack of support. At the same time, management grew increasingly upset with the team spending time on a project they didn't support. Eventually Peddle was sent an official memo from management telling him to stop working on the low-cost design. In response, much of the original 6800 design team resigned en masse and went looking for a company that would be interested in building their new design.[1]
The team was soon in negotiations with MOS Technology, at that time a small fabrication facility who produced chips for 3rd parties with limited internal design capability. The company had originally been set up by Allen-Bradley as a second-source for Texas Instruments calculator chips, but had since branched out to produce runs for a number of different companies. One of their recent products at the time was a single-chip implementation of the popular Pong video game. The existing MOS engineers were not pleased to find an entire new team parachuted into their company. They were even more upset when they learned that the team would be cut in on part of any profits the new design generated.[1]
At MOS, the Motorola team quickly designed the 6501, the first member of the 65xx series of microprocessors and the first to be sold for US$25. The new processor was designed to be pin-compatible with the 6800. This allowed it to be plugged into motherboards designed for the Motorola processor, like the MEK6800D2, although its instruction set was different. It offered several addressing modes not available on the 6800. The 6501 is an eight-bit microprocessor operating at 1 MHz using an NMOS process. It has a 16-bit address bus capable of addressing 64 kB of memory.[3][4]
Motorola sued immediately, and MOS agreed to stop producing the 6501 and went back to the drawing board. The result was the "lawsuit-compatible" 6502, which was by design unusable in a 6800 motherboard but otherwise identical to the 6501. Motorola had no objection to this version. MOS was forced to pay the legal costs and promise to destroy every 6501 they had manufactured.[5] The 6502 also added a two-phase clock generator, so it only needed a single phase clock input, simplifying system design.
However, this left MOS with the problem of getting developers to try their processor, so Peddle designed the MDT-650 (for "microcomputer development terminal") single-board computer. Another group inside the company designed the KIM-1, which was sold semi-complete and could be turned into a usable system with the addition of a 3rd party computer terminal and compact cassette drive. Much to their surprise, the KIM-1 sold well to hobbyists and tinkerers, as well as to the engineers it was intended for. The related Rockwell AIM 65 control/training/development system also did well. The software in the AIM 65 was based on that in the MDT. Another roughly similar product was the Synertek SYM-1.
The 6502 was introduced at US$25 ($102.02 in 2012) at the Wescon show in September 1975. The company had an off-floor suite with a big jar full of the chips. However with this early run they only had a handful of working ones. To give the appearance of larger quantities, the bottom of the jar was stuffed with defective chips, and only the ones at the top of the jar worked.[6] At the same show the 6800 and Intel 8080 were selling for US$179.[7] At first many people thought the new chip's price was a hoax or a mistake, but while the show was still ongoing both Motorola and Intel had dropped their chips to US$69.[8][9] These price reductions legitimized the 6502, which started selling by the hundreds.[6]
One of the first "public" uses for the design was the Apple I computer, introduced in 1976. The 6502 was next used in the Atari 2600, Commodore PET and the Apple II, all released in 1977. It was later used in the Atari home computers, the BBC Micro family, the Commodore VIC-20 and a large number of other designs both for home computers and business, such as Ohio Scientific and Oric. The 6510, a direct successor of the 6502 with a digital I/O port and a tri-state address bus, was the CPU utilized in the Commodore 64 home computer. (Commodore's disk drive, the 1541, had a processor of its own—it too was a 6502.)
Another important use of the 6500 family was in video games. The first to make use was the Atari 2600 video game console. The 2600 used an offshoot of the 6502 called the 6507, which had fewer pins and, as a result, could address only 8 KB of memory. Millions of the Atari consoles would be sold, each with a MOS processor. Another significant use was by the Nintendo Famicom, a Japanese video game console. Its international equivalent, the Nintendo Entertainment System, also used the processor. The 6502 used in the NES was a second source version by Ricoh, a partial system-on-a-chip, that lacked the binary-coded decimal mode but added 22 memory-mapped registers (and on-die hardware) for sound generation, joypad reading, and sprite list DMA. Called 2A03 in NTSC consoles and 2A07 in PAL consoles (the difference being the memory divider ratio and a lookup table for audio sample rates), this processor was produced exclusively for Nintendo.
The MOS Technology 6502 is a 16 µm[10] process technology chip with 3510 transistors and a die size of 21 mm².[11] The 6502 is an 8-bit processor with a 16-bit address bus. The internal logic runs at the same speed as the external clock rate, but despite the slow clock speeds (typically in the neighborhood of 1 to 2 MHz), the 6502's performance was actually competitive with other CPUs using significantly faster clocks. This is partly due to a simplistic state machine implemented by combinatorial (clockless) logic to a greater extent than in many other designs; the two phase clock (supplying two synchronizations per cycle) can thereby control the whole machine-cycle directly. Like most simple CPUs of the era, the dynamic NMOS 6502 chip was not sequenced by a microcode ROM but used a PLA (which occupied about 15% of the chip area) for instruction decoding and sequencing. Like most eight-bit microprocessors, the chip does some limited overlapping of fetching and execution.
The low clock frequency moderated the speed requirement of memory and peripherals attached to the CPU, as only about 50% of the clock cycle was available for memory access (due to the asynchronous design, this percentage varied strongly among chip versions). This was critical at a time when affordable memory had access times in the range 450 - 250 ns. The original NMOS 6502 was minimalistically engineered and efficiently manufactured and therefore cheap—an important factor in getting design wins in the very price-sensitive game console and home computer markets.
Like its precursor, the Motorola 6800, the 6502 has very few registers. At the time the processor was designed, the number of transistors that could be economically put on a chip was very constrained (around a few thousand), so it made sense to rely on RAM instead of allocating expensive NMOS chip area for CPU registers.
The 6502's registers included one 8-bit accumulator register (A), two 8-bit index registers (X and Y), an 8-bit processor status register (P), an 8-bit stack pointer (S), and a 16-bit program counter (PC). The stack's address space was hardwired to memory page $01, i.e. the address range $0100–$01FF (256–511). Software access to the stack was done via four implied addressing mode instructions, whose functions were to push or pop (pull) the accumulator or the processor status register. The same stack was also used for subroutine calls via the JSR (Jump to Subroutine) and RTS (Return from Subroutine) instructions, and for interrupt handling.
The chip used the index and stack registers effectively with several addressing modes, including a fast "direct page" or "zero page" mode, similar to that found on the PDP-8, that accessed memory locations from addresses 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address)—code for the 6502 used the zero page much as code for other processors would have used registers. On some 6502-based microcomputers with an operating system, the OS would use most of zero page, leaving only a handful of locations for the user.
Addressing modes also included implied (1 byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Absolute mode was a general-purpose mode. Branch instructions used a signed 8-bit offset relative to the instruction after the branch; the numerical range -128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode used the accumulator as an effective address, and did not need any operand data. Immediate mode used an 8-bit literal operand.
The indirect modes were useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register was added to a 16-bit base address in zero page which was located by a single byte following the opcode. The Y register was therefore an index-register in the sense that it was used to hold an actual index (as opposed to the X register in the 6800 where a base address was directly stored and to which an immediate offset could be added). Incrementing the index register to walk the array byte-wise took only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation was found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acted as a set of 128 additional (though very slow) address registers.
The 6502 is capable of performing addition and subtraction in binary or binary coded decimal. Placing the CPU into BCD mode with the SED instruction results in decimal arithmetic, in which $99 + $01 would result in $00 and the carry flag being set. In binary mode (CLD), the same operation would result in $9A and the carry flag being cleared. Other than Atari BASIC, BCD mode was seldom used in home computer applications.
A Byte magazine article once referred to the 6502 as "the original RISC processor", due to its efficient, simplistic, and nearly orthogonal instruction set (most instructions work with most addressing modes), as well as its 256 zero-page "registers". The 6502 is technically not a RISC design, however, as arithmetic operations can read any memory cell (not only zero-page), and some instructions (inc, rol etc.) even modify memory, contrary to the basic load/store philosophy of RISC. Furthermore, orthogonality is equally often associated with "CISC". However, the 6502 performed reasonably well compared to other contemporary processors such as the Z80, which used a much faster clock rate, and the 6502 has been credited as being inspirational to RISC processors such as the ARM.[12] However, the inspiration from the 6502 was related to the simple implementation, rather than the architecture, which is very different than that of the ARM. Sophie Wilson, who designed the instruction set for the ARM, has stated that the 6502 has little in common with the ARM processor.[13]
See the Hello world! article for a simple but characteristic example of 6502 assembly language.
The processor's non-maskable interrupt (NMI) input is edge sensitive, which means that if the source of an NMI holds the line low, further NMIs after the first are effectively disabled.
The simultaneous assertion of the NMI (non-maskable) and IRQ (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will immediately respond to IRQ, as IRQ is level sensitive. Thus a sort of built-in interrupt priority was established in the 6502 design.
The "Break" flag of the processor is very different from the other flag bits. It has no flag setting, resetting, and testing instructions of its own, and is not handled by the PHP and PLP instructions either. It exists only on the stack, where BRK and PHP always write a 1, while IRQ and NMI always write a 0.
The "SO" input pin, when asserted, would set the processor's overflow status bit (deasserting it does not clear the overflow bit, however). This can be used by a high-speed polling device driver, which can poll the hardware once in only three cycles by using a Branch-on-oVerflow-Clear (BVC) instruction that branches to itself; for example the Commodore 1541 and other Commodore floppy disk drives use it to detect as quickly as possible whether the serializer is ready to accept or provide another byte of disk data, as a normal test-and-branch loop takes seven cycles which is too slow in that particular application. Obviously great care must be used in the device driver and the associated system design, as spurious assertion of the overflow bit could ruin arithmetic processing.
There were several variants of the NMOS 6502 produced:
The MOS Technology 6512 was used in the BBC Micro B+64, and relied on an external clock. (The 6502 used an internal clock generator to generate the Phase 1 and Phase 2 clocks.) This was used to advantage in some designs where the clocks could be run asymmetrically, increasing overall CPU performance.
The Western Design Center designed and produced the 65C816 processor, a 16-bit successor to the 65C02, as well as a hybrid offshoot called the 65C802 which was a 65C816 core with a 64 KB address space in a 65(C)02 pin-compatible package—it could be plugged into a 6502 board and would function as a 65C02, or it could be configured via software to expose its 16 bit accumulator and index registers. Few 65C802 parts were sold, and the chip is no longer produced.
The 65C816 was the core of the widely popular Super Nintendo Entertainment System, and the Apple IIGS. The 65C816 is still widely used, both as a discrete processor and as the core of a microcontroller.
Mitsubishi (now Renesas Technology) made a line of 16-bit microcontrollers with an architecture very similar to the 65816, though it was not 100% compatible.
Synertek published a data sheet and application notes on the SY6516, a 16-bit derivative of the 6502, but the part was never introduced.
Many users of 1 MHz 6502-based systems soon wished their computers could go faster. As the 6502 is externally-clocked, upgrading the speed involved more than dropping a faster chip into the processor socket; many other components would also need to be modified. To meet user demand, a number of companies sold hardware to speed up those systems. These "accelerators" included a modicum of high-speed RAM and glue circuitry used to synchronize the faster processor with the computer's original RAM and its peripherals. For example, the Apple II floppy disk relied on software accessing the controller's I/O registers with critical timing; Apple II accelerators were therefore designed to fall back to 1 MHz during disk access. The first accelerators were circuit boards; some later accelerators (such as the Zip Chip) miniaturized the processor and support circuits to fit into a DIP package that was plug-compatible with the original processor.
In the science fiction movie The Terminator (1984), starring Arnold Schwarzenegger, the audience at one point is treated to a view through the T-800 Model-101 robot character's eye/camera display with some 6502 assembly/machine code program fragments scrolling down the screen. The program was listing the Apple DOS 3.3 disassembled program listing. Also shown is the output from a run of an Apple checksum program called KEY PERFECT 4.0, published in Nibble magazine.
Bender, a fictional "industrial robot" manufactured in 2998, and a main character in the animated TV series Futurama created by Matt Groening, was revealed to have a 6502 as his "brain" in the episode "Fry and the Slurm Factory". David X. Cohen (the head writer and executive producer of Futurama) has claimed in an interview with IEEE Spectrum that he and friends David Borden and David Schiminovich wrote an assembly language compiler (for a custom language they created named "FLEET") for the Apple II Plus, which uses the 6502, while at high school, and confirmed that this led him to include the reference in the show. [17]
General information:
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Emulators and simulators:
Early 6502 computers:
Hardware accelerators:
Hardware:
This article was originally based on material from the Free On-line Dictionary of Computing, which is licensed under the GFDL.
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