A low-dropout or LDO regulator is a DC linear voltage regulator which can operate with a very small input–output differential voltage.[1] The advantages of a low dropout voltage include a lower minimum operating voltage, higher efficiency operation and lower heat dissipation.[2]
The main components are a power FET and a differential amplifier (error amplifier). One input of the differential amplifier monitors the fraction of the output determined by the resistor ratio of R1 and R2. The second input to the differential amplifier is from a stable voltage reference (bandgap reference). If the output voltage rises too high relative to the reference voltage, the drive to the power FET changes to maintain a constant output voltage.
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The adjustable low-dropout regulator debuted on April 12, 1977 in an Electronic Design article entitled "Break Loose from Fixed IC Regulators". The article was written by Robert Dobkin, an IC designer then working for National Semiconductor. Because of this, National Semiconductor claims the title of "LDO inventor".[3] Dobkin later left National in 1981 to found Linear Technology where he is currently chief technology officer.[4]
Current advances in semiconductor technology made possible to significantly reduce voltage drop on all linear voltage regulators, so producers today advertise almost everything as low-dropout. For example, the AS1117 is advertised as low drop out even if it uses same topology as 78xx series.
Low-dropout (LDO) regulators work in the same way as all linear voltage regulators. The main difference between LDO and non-LDO regulators is their schematic topology. Instead of an emitter follower topology, Low-dropout regulators utilize open collector or open drain topology. This enables transistor saturation, which limits the voltage drop to only the saturation voltage.
If a bipolar transistor is used however, significant additional power is lost to control it, when non-LDO regulators take that power from voltage drop itself. For high voltages under very low In-Out difference there will be significant power loss in control circuit. [5]
Because the power control element is working as an inverter, another inverting amplifier is required to control it, which increases schematic complexity compared to a simple voltage stabilizer.
Power FETs may be preferable to reduce power consumption, but this significantly increases price and poses problems when the regulator is used for low input voltage, because FETs usually require 5 to 10V to open completely.
Among other important characteristics is the quiescent current (the current flowing through the system when no load is present), which creates a difference between the input and output currents. The series pass element, topologies, and ambient temperature are the primary contributors to quiescent current. Quiescent current and input–output drop limit the efficiency of LDO regulators and should thus be minimized.