Input/output Buffer Information Specification

IBIS (Input/output Buffer Information Specification) is a method for integrated circuit vendors to provide information about the input/output buffers of their product to their prospective customers without revealing the intellectual property of their implementation and without requiring proprietary encryption keys.[1] The model is generated in text format and consists of a number of tables that captures current vs. voltage (IV) and voltage vs. time (Vt) characteristics of the buffer, as well as the values of certain parasitic components. In other words, it is a template (standard, data exchange format, etc.) for exchanging modeling information among semiconductor device suppliers, simulation software suppliers, and end users.

IBIS models are generally used in lieu of SPICE models, to perform various board level signal integrity (SI) simulations and timing analyses. IBIS models could be used to verify signal integrity requirements, especially for high speed products.

Contents

History

Intel initiated IBIS in the early 1990s.[2] Intel needed to have all of its divisions to present a common standardized model format to its external customers. This prompted Intel to solicit EDA vendors to participate in the development of a common model format. The first IBIS model, version 1.0, was aimed at describing CMOS circuits and TTL I/O buffers.

As IBIS evolved with the participation of more companies and industry members, an IBIS Open Forum was created to promote the application of IBIS as a simulation tool format and to make sure that a standard exists. Many semiconductor vendors supply IBIS models[3][4] and many EDA vendors sell IBIS-compliant software tools.[5][6] In 1995 the IBIS Open Forum teamed with the American National Standards Institute/Electronic Industries Alliance (ANSI/EIA). IBIS version 2.1 was the first version released by the new alliance. It added the ability to simulate ECL and PECL buffers as well as differential lines. IBIS 3.2 allows for a package model description along with an electrical board description. IBIS Version 5.0 was ratified by the IBIS Open Forum on August 29, 2008.[7] Compared to the previous version (IBIS 4.2, ANSI/EIA-656-B), it adds a new flow based not on SPICE transient but on a channel simulator (called algorithmic model application program interface or AMI flow), power integrity, and EMC checking features. For power integrity, it uses Touchstone 2.0[8] S-parameter files with per-port reference impedance specification.

Today the IBIS Open Forum is an official subcommittee of TechAmerica.[9]

Evolution

IBIS is an evolving standard with many proposed changes submitted to IBIS Open Forum for consideration.[10] Proposed changes are called BIRDs (Buffer Issue Resolution Documents), a play on the original meaning of ibis namely a type of bird.

Notes

  1. ^ "IBIS Open Forum: Frequently Asked Questions: What is this IBIS stuff anyhow?". http://www.eda.org/ibis/home/faq/#_1. 
  2. ^ Mark Chang (PDF). Introduction to IBIS Modeling of Fiber Optic Transceivers. Agilent Technologies. http://cp.literature.agilent.com/litweb/pdf/5990-3107EN.pdf. Retrieved 2010-12-23. 
  3. ^ "IBIS Model Suppliers". http://www.eda.org/ibis/home/models/. 
  4. ^ "Teraspeed IBIS resources: Semiconductor Vendor IBIS Models". http://www.teraspeed.com/ibis_resources.html#manufacturer. 
  5. ^ "2011 ANSI/EIA-656B IBIS Committee Participation Roster". http://www.eda.org/ibis/roster/. 
  6. ^ "Modeling Utilities: EDA and Semiconductor Vendor IBIS Content". http://www.teraspeed.com/ibis_resources.html#utilities. 
  7. ^ "IBIS Open Forum - Specifications". http://www.eda.org/ibis/home/specs/. 
  8. ^ "Touchstone® File Format Specification Version 2.0". http://www.eda.org/pub/ibis/touchstone_ver2.0/touchstone_ver2_0.pdf. 
  9. ^ "IBIS Open Forum: Frequently Asked Questions: How do I become an IBIS Forum Member?". http://www.eda.org/ibis/home/faq/#_18. 
  10. ^ "Buffer Issue Resolution Documents (BIRD)". http://www.vhdl.org/pub/ibis/birds/. 

External links