| Type | Public |
|---|---|
| Traded as | NASDAQ: ALTR NASDAQ-100 Component S&P 500 Component |
| Industry | Integrated Circuits |
| Founded | 1983 |
| Headquarters | San Jose, California, U.S. |
| Key people | John P. Daane (Chairman, President and CEO) |
| Products | FPGAs, CPLDs, Embedded Processors, ASICs |
| Revenue | US$ 1.954 billion (2010)[1] |
| Operating income | US$ 867.3 million (2010)[1] |
| Net income | US$ 782.9 million (2010)[1] |
| Total assets | US$ 3.760 billion (2010)[1] |
| Total equity | US$ 2.324 billion (2010)[1] |
| Employees | 2,666 (December 2010)[1] |
| Website | Altera.com |
Altera Corporation (NASDAQ: ALTR) is a Silicon Valley manufacturer of PLDs (programmable logic devices). The company offered its first programmable logic device in 1984.[2] PLDs can be reprogrammed during the design cycle as well as in the field to perform multiple functions, and they support a fairly fast design process. Altera's main products are the Cyclone, Arria GX and Stratix series of FPGAs (field-programmable gate arrays), the MAX series of CPLDs (complex programmable logic devices), the HardCopy series of ASICs (ASIC) and Quartus II design software.
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The Stratix series FPGAs are the company's largest, highest bandwidth devices, with up to 1.1 million logic elements, integrated transceivers at up to 28 Gbit/s, up to 1.6 Tbit/s of serial switching capability, up to 1,840 GMACs of signal-processing performance, and up to 7 x72 DDR3 memory interfaces at 800 MHz. Cyclone series FPGAs are the company's lowest cost, lowest power FPGAs, with variants offering integrated transceivers up to 3.125 Gbit/s. In between these two device families are Arria series FPGAs, which provide a balance of performance, power, and cost for mid-range applications such as remote radio heads, video conferencing equipment, and wireline access equipment. Arria FPGAs have integrated transceivers up to 6.375 Gbit/s.
Altera offers a design flow based on HardCopy ASICs, which transitions the FPGA design, once finalized, to a form which is not alterable. This design flow reduces design security risks as well as costs for higher volume production. Design engineers can prototype their designs in Stratix series FPGAs, and then migrate these designs to HardCopy ASICs when they're ready for volume production.
The unique design flow makes hardware/software co-design and co-verification possible. The flow has been benchmarked to deliver systems to market 9 to 12 months faster, on average, than with standard-cell solutions. Design engineers can employ a single RTL, set of intellectual property (IP) cores, and Quartus II design software for both FPGA and ASIC implementations. Altera's HardCopy Design Center manages test insertion.[3]
In April 2010, Altera introduced the FPGA industry's first 28-nm device, the Stratix V FPGA, available with transceivers at speeds up to 28 Gbit/s. This device family has more than 1 million logic elements, up to 53 Mb of embedded memory, up to 7 x72 DDR3 DIMMs at 800 MHz, 1.6-Gbit/s LVDS performance, and up to 3,680 variable-precision DSP blocks. In August 2011, Altera began shipping 28-nm Stratix V GT devices featuring 28-gigabits-per-second (Gbps) transceivers.[4]
The devices also feature some unique features. Embedded HardCopy Blocks harden standard or logic-intensive applications, increasing integration and delivering twice the density without a cost or power penalty. Altera has developed a user friendly method for partial reconfiguration, so core functionality can be changed easily and on the fly. And there is a path to HardCopy V ASICs, when designs are ready for volume production. Also, Altera’s 28nm FPGAs aim to reduce power requirements to 200 mW per channel.[4]
In May 2008, Altera introduced the industry's first 40-nm programmable logic devices: the Stratix IV FPGAs and HardCopy IV ASICs. Both devices are available with integrated transceiver options. Since then, the company has also introduced Stratix IV GT FPGAs, which have 11.3-Gbit/s transceivers for 40G/100G applications, and Arria II GX FPGAs, which have 3.75-Gbit/s transceivers for power- and cost-sensitive applications.
Semiconductors manufactured on a 40-nm process node address many of the industry's key challenges, including power consumption, device performance, and cost. Altera's devices are manufactured using techniques such as 193-nm immersion lithography and technologies such as extreme low-k dielectrics and strained silicon. These techniques and technologies bring enhancements to device performance and power efficiency.
Altera and its partners offer an array of intellectual property (IP) cores that serve as building blocks that design engineers can drop into their system designs to perform specific functions. IP cores eliminate some of the time-consuming tasks of creating every block in a design from scratch.
Altera offers an embedded portfolio with a broad selection of soft processor cores.
All of Altera's devices are supported by a common design environment, Quartus II design software. Quartus II software is available in a subscription-based edition and a free Web-based edition. It includes a number of tools to foster productivity. Some Quartus II software features include:
Altera's largest competitor is FPGA founder and market-share leader Xilinx, who has been a long-time rival of Altera.[5]
The two companies closest competitor is Lattice Semiconductor, who represents less than ten percent of the market.[5]
Other FPGA makers, Actel (now Microsemi) and QuickLogic, sell to a lower-end market segment that Altera mostly does not address.
In broader terms, Altera competes with ASIC, Structured ASIC, and Zero Mask-Charge ASIC companies like eASIC. Moore's Law and improving software tools are rapidly expanding FPGAs' potential markets.