90 nanometer

The 90 nm process refers to the level of CMOS process technology that was reached in the 2002–2003 timeframe, by most leading semiconductor companies, like Intel, AMD, Infineon, Texas Instruments, IBM, and TSMC.

The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).

The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

Contents

Example: Elpida 90 nm DDR2 SDRAM process[1]

Processors using 90 nm process technology

See also

References

  1. ^ Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report

External links

Preceded by
130 nm
CMOS manufacturing processes Succeeded by
65 nm